Synchronous multi-clock protocol converter

Abstract

Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

1. A method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising:
 receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; 
 propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain; 
 receiving second fast data from the fast clock domain during a second fast clock cycle that is different from the first fast clock cycle, wherein the second fast clock cycle is at least partially in the first slow clock cycle; and 
 refraining from propagating the second fast data to the slow clock domain for a period between the second fast clock cycle and another first full fast clock cycle in a second slow clock cycle. 
 
     
     
       2. The method of  claim 1 , further comprising:
 propagating, during the another first full fast clock cycle in the second slow clock cycle, the received second fast data to the slow clock domain. 
 
     
     
       3. The method of  claim 2 , wherein said propagating the received second fast data further comprises:
 enabling a drive mask signal during the another first full fast clock cycle in the second slow clock cycle; and 
 propagating the received second fast data to the slow clock domain based at least in part on the drive mask signal. 
 
     
     
       4. The method of  claim 2 , wherein the first slow clock cycle and the second clock cycle are two consecutive slow clock cycles of the slow clock signal. 
     
     
       5. A method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising:
 receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and 
 propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain; 
 wherein said propagating the received first fast data further comprises: 
 enabling a drive mask signal during the first full fast clock cycle in the first slow clock cycle; and 
 propagating the received first fast data to the slow clock domain based at least in part on the drive mask signal. 
 
     
     
       6. A method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising:
 receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; 
 propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain; 
 receiving a fast valid signal during the first fast clock cycle and a second fast clock cycle, wherein the second fast clock cycle is at least partially in the first slow clock cycle; 
 propagating the received fast valid signal, as a slow valid signal, to the slow clock domain during the first fast clock cycle; and 
 refraining from propagating the received fast valid signal to the slow clock domain during the second fast clock cycle. 
 
     
     
       7. The method of  claim 6 , further comprising:
 receiving a slow ready signal from the slow clock domain during the first slow clock cycle; and 
 generating, during at least a part of a last full fast clock cycle in the first slow clock cycle, a fast ready signal based at least in part on the slow ready signal and slow valid signal. 
 
     
     
       8. The method of  claim 7 , further comprising:
 determining a completion of transfer of the first fast data from the fast clock domain to the slow clock domain, based at least in part on the generated fast ready signal and the fast valid signal. 
 
     
     
       9. The method of  claim 7 , wherein generating the fast ready signal further comprises:
 generating the fast ready signal such that:
 the fast ready signal begins after a beginning of the last full fast clock cycle in the first slow clock cycle; and 
 the fast ready signal ends before an end of the last full fast clock cycle in the first slow clock cycle. 
 
 
     
     
       10. A fast to slow (F2S) bus converter for transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the fast clock signal including a plurality of fast clock cycles, and the slow clock signal including a plurality of slow clock cycles, the F2S bus converter comprising:
 a first latch configured to propagate, during a first fast clock cycle, a first fast data from the fast clock domain to the slow clock domain, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and 
 a second latch configured to propagate a fast valid signal to the slow clock domain during the first fast clock cycle. 
 
     
     
       11. The F2S bus convertor of  claim 10 , wherein the first latch is further configured to:
 receive the first fast data from the fast clock domain during the first fast clock cycle; 
 receive a drive mask signal that is enabled during the first fast clock cycle; and 
 propagate, during the first fast clock cycle, the received first fast data to the slow clock domain based at least in part on receiving the drive mask signal. 
 
     
     
       12. The F2S bus convertor of  claim 11 , wherein the first latch is further configured to:
 receive second fast data from the fast clock domain during a second fast clock cycle that is different from the first fast clock cycle, wherein the second fast clock cycle is at least partially in the first slow clock cycle; 
 refrain from propagating the second fast data to the slow clock domain for a period between the second fast clock cycle and another first full fast clock cycle in a second slow clock cycle; and 
 propagate, during the another first full fast clock cycle in the second slow clock cycle, the received second fast data to the slow clock domain. 
 
     
     
       13. The F2S bus convertor of  claim 11 , wherein the second latch is further configured to:
 receive the fast valid signal during the first fast clock cycle and during a second fast clock cycle, wherein the second fast clock cycle is at least partially in the first slow clock cycle; 
 propagate the received fast valid signal, as a slow valid signal, to the slow clock domain during the first fast clock cycle; and 
 refrain from propagating the received fast valid signal to the slow clock domain during the second fast clock cycle. 
 
     
     
       14. A method of transferring data from a slow clock domain that is driven by a slow clock signal to a fast clock domain that is driven by a fast clock signal, the method comprising:
 receiving slow data from the slow clock domain during a slow clock cycle; 
 refraining from propagating the slow data to the fast clock domain during a first fast clock cycle that is at least partially in the slow clock cycle, wherein the first fast clock cycle is not a last full fast clock cycle in the slow clock cycle; and 
 propagating, during at least a part of a second fast clock cycle, the received slow data to the fast clock domain, wherein the second fast clock cycle is a last full fast clock cycle in the slow clock cycle. 
 
     
     
       15. The method of  claim 14 , further comprising:
 receiving a slow valid signal from the slow clock domain during the slow clock cycle based at least in part on receiving the slow data during the slow clock cycle; 
 refraining from propagating the slow valid signal to the fast clock domain during the first fast clock cycle; and 
 output, during at least a part of the second fast clock cycle, the received slow valid signal to the fast clock domain. 
 
     
     
       16. The method of  claim 14 , further comprising:
 receiving a fast ready signal from the fast clock domain during the first fast clock cycle and the second fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in the slow clock cycle; 
 propagating, during the first fast clock cycle, the received fast ready signal to the slow clock domain as a slow ready signal; and 
 refraining from propagating the fast ready signal to the slow clock domain during the second fast clock cycle. 
 
     
     
       17. The method of  claim 16 , further comprising:
 generating a fast valid signal during at least a part of the second fast clock cycle, such that the fast valid signal begins after a beginning of the second fast clock cycle and ends before an end of the second fast clock cycle; and 
 signing a contract in the fast clock domain, indicating a completion of transfer of the slow data from the slow clock domain to the fast clock domain, based at least in part on the fast ready signal and the fast valid signal.