Inventor
STOLER GIL
IL30 patents
⚠️ This page may combine multiple inventors who share the name “STOLER GIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AMAZON TECH INC
12 patentsUS10691576B1Jun 23, 2020
Multiple reset types in a system
AMAZON TECH INC20 citations94
US9628211B1Apr 18, 2017
Clock generation with non-integer clock dividing ratio
AMAZON TECH INC22 citations94
US10019546B1Jul 10, 2018
Modular system on chip configuration system
AMAZON TECH INC16 citations92
US10746792B1Aug 18, 2020
Debug mechanisms for a processor circuit
AMAZON TECH INC9 citations84
US10185678B1Jan 22, 2019
Universal offloading engine
AMAZON TECH INC11 citations84
US10078568B1Sep 18, 2018
Debugging a computing device
AMAZON TECH INC12 citations84
US9800400B1Oct 24, 2017
Clock phase alignment in data transmission
AMAZON TECH INC8 citations84
US10061700B1Aug 28, 2018
System and method for managing transactions
AMAZON TECH INC1 citations63
US9411731B2Aug 9, 2016
System and method for managing transactions
AMAZON TECH INC2 citations63
US10635589B2Apr 28, 2020
System and method for managing transactions
AMAZON TECH INC0 citations52
US10489546B1Nov 26, 2019
Modular system on chip configuration system
AMAZON TECH INC0 citations52
US10044456B1Aug 7, 2018
Clock generation with non-integer clock dividing ratio
AMAZON TECH INC0 citations52
ROHANA TAREK
5 patentsUS8332590B1Dec 11, 2012
Multi-stage command processing pipeline and method for shared cache access
ROHANA TAREK24 citations91
US8117395B1Feb 14, 2012
Multi-stage pipeline for cache access
ROHANA TAREK26 citations91
US8499123B1Jul 30, 2013
Multi-stage pipeline for cache access
ROHANA TAREK4 citations61
US8688911B1Apr 1, 2014
Transparent processing core and L2 cache connection
ROHANA TAREK0 citations51
US8484421B1Jul 9, 2013
Cache pre-fetch architecture and method
ROHANA TAREK0 citations51
MARVELL ISRAEL MISL LTD
5 patentsUS7652516B2Jan 26, 2010
Apparatus and method for generating a clock signal
MARVELL ISRAEL MISL LTD15 citations82
US7932768B2Apr 26, 2011
Apparatus and method for generating a clock signal
MARVELL ISRAEL MISL LTD5 citations72
US8938585B1Jan 20, 2015
Transparent processing core and L2 cache connection
MARVELL ISRAEL MISL LTD2 citations61
USRE46766EMar 27, 2018
Cache pre-fetch architecture and method
MARVELL ISRAEL MISL LTD0 citations51
US8954681B1Feb 10, 2015
Multi-stage command processing pipeline and method for shared cache access
MARVELL ISRAEL MISL LTD0 citations51