Imager devices having differing gate stack sidewall spacers, method for forming such imager devices, and systems including such imager devices

Abstract

Imager devices have a sensor array and a peripheral region at least partially surrounding the sensor array. At least one transistor in the peripheral region has a gate stack sidewall spacer that differs in composition from a gate stack sidewall spacer on at least one transistor in the sensor array. Imaging systems include such an imager device configured to communicate electrically with at least one electronic signal processor and at least one memory storage device. Methods of forming such imager devices include providing layers of oxide and nitride materials over transistors on a workpiece, and using etching processes to form gate stack sidewall spacers on the transistors.

What is claimed is: 
     
       1. An imager device, comprising:
 a sensor array comprising a plurality of array transistors substantially free of silicide material and each having gate stack sidewall spacers substantially free of nitride material; and 
 a peripheral region at least partially surrounding the sensor array, the peripheral region comprising a plurality of peripheral transistors, each comprising:
 at least one gate stack sidewall spacer comprising nitride material; and 
 silicide material on at least a portion of at least one of a gate, a source, and a drain of each respective peripheral transistor, wherein the plurality of array transistors comprises:
 a plurality of reset transistors; 
 a plurality of source follower transistors; and 
 a plurality of row select transistors, wherein the peripheral region is free of the plurality of array transistors. 
 
 
 
     
     
       2. The imager device of  claim 1 , wherein the array transistors each have gate stack sidewall spacers comprising an oxide material. 
     
     
       3. The imager device of  claim 1 , wherein the peripheral transistors of the plurality each comprise at least one gate stack sidewall spacer having a first region comprising a nitride material and a second region comprising an oxide material. 
     
     
       4. The imager device of  claim 3 , wherein the nitride material is disposed between the oxide material and at least a portion of a gate. 
     
     
       5. The imager device of  claim 4 , wherein the at least a portion of the gate comprises the silicide material. 
     
     
       6. The imager device of  claim 4 , wherein the nitride material is disposed between the oxide material and at least a portion of at least one of a source and a drain. 
     
     
       7. The imager device of  claim 5 , wherein the at least a portion of at least one of a source and a drain comprises the silicide material. 
     
     
       8. An imager device, comprising:
 a sensor array comprising a plurality of array transistors, at least one array transistor of the plurality having at least one gate stack sidewall spacer substantially free of nitride material; and 
 a peripheral region at least partially surrounding the sensor array, the peripheral region comprising a plurality of peripheral transistors, at least one peripheral transistor of the plurality having at least one gate stack sidewall spacer comprising nitride material, wherein the plurality of array transistors comprises:
 a plurality of reset transistors; 
 a plurality of source follower transistors; and 
 a plurality of row select transistors, wherein the peripheral region is free of the plurality of array transistors.