Reducing latency in data transfer between asynchronous clock domains

Abstract

A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C 1 and a second clock domain operating at a second clock frequency C 2 . In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C 3 , which, in one embodiment, is greater than and a whole number multiple of C 2 . Preferably, C 3 is an even whole number multiple of C 2 . In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C 2 , and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C 3 , and clock signals A and B are source synchronized.

What is claimed is: 
     
       1. A method of transmitting data between a first clock domain operating at a first clock frequency C 1  and a second clock domain operating at a second clock frequency C 2 , the method comprising:
 transmitting the data from the first domain, through a synchronization section of an interfacing circuitry, and to the second domain; and 
 operating the synchronization section of the interfacing circuitry at a third frequency C 3 , wherein C 3  is a whole number multiple of C 2 , wherein C 3  is less than C 1  and wherein C 3  is at least 90% of C 1 . 
 
     
     
       2. A method according to  claim 1 , wherein the step of operating the synchronization section of the interfacing circuitry comprises operating said synchronization section of the interfacing circuitry at the third frequency C 3 , wherein C 3  is an even whole number multiple of C 2 . 
     
     
       3. A method according to  claim 1 , wherein a clock signal A is used to operate the second clock domain at frequency C 2 , and a clock signal B is used to operate a second section of the interfacing circuitry at frequency C 3 , each of the clock signals A and B have regular, active edge portions, and each occurrence of one of the active edge portions of clock signal A is aligned with one of the active edge portions of clock signal B. 
     
     
       4. A method according to  claim 3 , wherein clock signals A and B are source synchronized. 
     
     
       5. A method according to  claim 4 , wherein:
 the synchronization section of the interfacing circuitry includes first and second registers; and 
 the step of operating the synchronization section of the interfacing circuitry at frequency C 3  includes the step of operating the first and second registers at frequency C 3 . 
 
     
     
       6. A method according to  claim 5 , wherein the interfacing circuitry includes a third register for receiving signals from the first domain, and the first and second registers are in series between the third register and the second clock domain. 
     
     
       7. A method according to  claim 6 , wherein the third register operates at frequency C 1 , and C 2  is substantially less than C 1 . 
     
     
       8. An interfacing circuitry for transmitting data between a first clock domain operating at a first clock frequency C 1  and a second clock domain operating at a second clock frequency C 2 , the interfacing circuitry comprising:
 a synchronization section for receiving data transmitted from the first clock domains; and including: 
 a data storage component for receiving said data and for transmitting the data to the second clock domain, and wherein said data storage component operates at a third frequency C 3  that is a whole number multiple of C 2 , wherein C 3  is an even whole number multiple of C 2 , wherein C 3  is less than C 1 , and wherein C 3  is at least 90% of C 1 . 
 
     
     
       9. An interfacing circuitry according to  claim 8 , wherein a clock signal A is applied to the second clock domain to operate said second clock domain at C 2 , a clock signal B is applied to the data storage component of the interfacing circuitry to operate said data storage component at C 3 . 
     
     
       10. An interface circuitry according to  claim 9 , wherein said clock signals A and B are source synchronized. 
     
     
       11. An interfacing circuitry according to  claim 8 , wherein:
 said data storage component includes first and second registers in series between said first clock domain and the second clock domain; and 
 clock signal B is applied to both the first and second registers to operate the first and second registers at frequency C 3 .