Inventor · disambiguated record
Anil Pothireddy
Also filed as: POTHIREDDY ANIL
19 granted patents·100 citations·filing 2007–2021
93Inventor score
Top patents by PatentIndex Score
19 records- 0187US8316187B2Cache memory including a predict bufferPOTHIREDDY ANIL·Filed 2008·Granted Nov 20, 2012·21 cites·8 claims
- 0282US7853738B2Efficient load/store buffer memory management in a computer communications network data transmission switchIBM·Filed 2008·Granted Dec 14, 2010·18 cites·14 claims
- 0381US7500132B1Method of asynchronously transmitting data between clock domainsIBM·Filed 2008·Granted Mar 3, 2009·15 cites·5 claims
- 0479US8984206B2Weightage-based scheduling for hierarchical switching fabricsIBM·Filed 2012·Granted Mar 17, 2015·6 cites·24 claims
- 0573US9479455B2Simultaneous transfers from a single input link to multiple output links with a timesliced crossbarIBM·Filed 2014·Granted Oct 25, 2016·3 cites·6 claims
- 0672US7916048B2Encoding a gray code sequence for an odd length sequenceIBM·Filed 2010·Granted Mar 29, 2011·5 cites·12 claims
- 0771US7667629B2Generating a gray code for an odd length sequence using a virtual spaceIBM·Filed 2008·Granted Feb 23, 2010·8 cites·16 claims
- 0868US8902899B2Input buffered switching device including bypass logicIBM·Filed 2013·Granted Dec 2, 2014·2 cites·20 claims
- 0967US7870448B2In system diagnostics through scan matrixIBM·Filed 2007·Granted Jan 11, 2011·6 cites·20 claims
- 1066US8902750B2Translating between an ethernet protocol and a converged enhanced ethernet protocolBASSO CLAUDE·Filed 2011·Granted Dec 2, 2014·2 cites·24 claims
- 1165US8161366B2Finite state machine error recoveryPOTHIREDDY ANIL·Filed 2007·Granted Apr 17, 2012·5 cites·22 claims
- 1265US8132036B2Reducing latency in data transfer between asynchronous clock domainsPOTHIREDDY ANIL·Filed 2008·Granted Mar 6, 2012·4 cites·11 claims
- 1362US7518535B1Generating a Gray code sequence for any even length using an intermediate binary sequenceIBM·Filed 2007·Granted Apr 14, 2009·5 cites·17 claims
- 1452US9207999B2Integrated link-based data recorder for semiconductor chipIBM·Filed 2013·Granted Dec 8, 2015·0 cites·12 claims
- 1552US9110742B2Integrated link-based data recorder for semiconductor chipIBM·Filed 2013·Granted Aug 18, 2015·0 cites·8 claims
- 1651US9467396B2Simultaneous transfers from a single input link to multiple output links with a timesliced crossbarIBM·Filed 2014·Granted Oct 11, 2016·0 cites·12 claims
- 1747US11579890B1Frame parser executing subsets of instructions in parallel for processing a frame headerSYNOPSYS INC·Filed 2021·Granted Feb 14, 2023·0 cites·20 claims
- 1842US9667564B2Implementing hierarchical high radix switch with timesliced crossbarIBM·Filed 2013·Granted May 30, 2017·0 cites·18 claims
- 1938US8589776B2Translation between a first communication protocol and a second communication protocolCALVIGNAC JEAN L·Filed 2011·Granted Nov 19, 2013·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →