Semiconductor circuits capable of mitigating unwanted effects caused by input signal variations

Abstract

Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

What is claimed is: 
     
       1. A semiconductor circuit, comprising:
 a main circuit receiving an input signal and comprising: 
 a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage; and 
 a replica circuit coupled to the main circuit to duplicate a distortion current through the first current source caused by a variation in the input signal and output the duplicated distortion current to the main circuit such that an output current of the main circuit is maintained at a constant, the replica circuit including a level shifter configured to level shift a second bias voltage of the replica circuit, the level shifter being coupled to the main circuit. 
 
     
     
       2. The semiconductor circuit as claimed in  claim 1 , wherein the main circuit comprises:
 a first transistor coupled between the first node and the first power voltage and comprising a control terminal coupled to the first bias voltage to serves as the first current source; and 
 a differential amplifier comprising:
 a loading unit; 
 a first transistor comprising a first terminal coupled to the loading unit, a second terminal coupled to the first current source, and a control terminal; and 
 a second transistor comprising a first terminal coupled to the loading unit, a second terminal coupled to the first current source, and a control terminal, wherein the control terminals of the first and second transistors for receiving the input signal. 
 
 
     
     
       3. The semiconductor circuit as claimed in  claim 1 , wherein the main circuit comprises:
 a first differential pair coupled between a loading unit and the first node, receiving the input signal; and 
 the first current source coupled between the first node and the first power voltage. 
 
     
     
       4. The semiconductor circuit as claimed in  claim 1 , wherein the replica circuit comprises:
 a second current source coupled between a second power voltage and a second node; 
 a second differential pair coupled between the second node and a third node, receiving the input signal; 
 a third current source coupled between the third node and the first power voltage, wherein bias control terminals of the first and third current sources are coupled to a constant bias voltage; and 
 a current mirror comprises two current output terminals coupled to the second node and the first node respectively. 
 
     
     
       5. The semiconductor circuit as claimed in  claim 4 , wherein the second current source is a constant current source. 
     
     
       6. The semiconductor circuit as claimed in  claim 1 , wherein the main circuit comprises a variable gain amplifier comprising:
 a second current source coupled between a second node and a second power voltage; 
 a first transistor coupled between the second node and a third node and comprising a control terminal coupled to a reference voltage; 
 a second transistor coupled between the third node and the first power voltage; 
 a third transistor comprising a first terminal coupled to the second node, and a second terminal; 
 a fourth transistor coupled between the second terminal of the third transistor and the first power voltage and comprising a control terminal coupled to the third node; 
 a fifth transistor comprising a first terminal coupled to the first power voltage, a control terminal coupled to the third node, and a second terminal; 
 sixth and seventh transistors coupled in series between the second power voltage and a fourth node to serve as the first current source, wherein the sixth transistor comprises a control terminal coupled to the first bias voltage; 
 a resistor coupled between the second node and the fourth node; 
 an eighth transistor coupled between the fourth node and a fifth node, and comprising a control terminal coupled to the input signal; 
 a ninth transistor coupled between the fifth node and the first power voltage; 
 a tenth transistor comprising a first terminal coupled to the fourth node, and a second terminal; 
 an eleventh transistor coupled between the second terminal of the tenth transistor and the first power voltage, and comprising a control terminal coupled to the fifth node; and 
 a twelfth transistor comprising a first terminal coupled to the first power voltage, a control terminal coupled to the fifth node, and a second terminal, wherein the second terminals of the fifth and twelfth transistors for outputting the output current. 
 
     
     
       7. A method for mitigating current variation in a semiconductor circuit, in which the semiconductor circuit comprises a main circuit receiving an input signal and comprising a first current source coupled between a first node and a first power voltage, the method comprising:
 duplicating, by a replica circuit, a distortion current through the first current source caused by a variation in the input signal; 
 adjusting, by a level shifter, a bias voltage of the replica circuit, the level shifter being coupled to the main circuit; and 
 outputting the duplicated distortion current to the main circuit such that an output current of the main circuit is maintained at a constant. 
 
     
     
       8. The method as claimed in  claim 7 , wherein a current increment is duplicated to serve as the distortion current and output to the main circuit when a voltage at the first node increases, and a current decrement is duplicated to serve as the distortion current and output to the main circuit when a voltage at the first node decreases, such that the first current is maintained at a constant. 
     
     
       9. A semiconductor circuit, comprising:
 a main circuit receiving an input signal and comprising a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage; and 
 a replica circuit coupled to the main circuit configured to duplicate a distortion current through the first current source caused by a variation in the input signal and output the duplicated distortion current to the main circuit such that an output current of the main circuit is maintained at a constant, the replica circuit comprising a differential pair coupled to a constant current source, the replica circuit including a level shifter connected directly to the output of the constant current source, the replica circuit configured to level shift a second bias voltage at the output of the constant current source, the level shifter being coupled to the main circuit.