Memory array and method for manufacturing and operating the same

Abstract

The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.

1. A memory array comprising:
 a plurality of word lines; 
 a charge trapping structure covering a surface of each of the word lines; 
 a plurality of trench channels, wherein the word lines and the trench channels are arranged parallel with each other and alternately arranged along a horizontal direction and each trench channel is separated from the adjacent word lines by the charge trapping structure; and 
 a plurality of bit lines located across the word lines, wherein the trench channels are electrically coupled to the bit lines. 
 
     
     
       2. The memory array of  claim 1 , wherein the word lines are isolated from the substrate by a dielectric layer formed on the substrate. 
     
     
       3. The memory array of  claim 2 , wherein the trench channels are isolated from the substrate by the dielectric layer. 
     
     
       4. The memory array of  claim 2 , wherein the material of the dielectric layer includes silicon oxide. 
     
     
       5. The memory array of  claim 1 , wherein a top level of each trench channel is lower than a top level of each word line. 
     
     
       6. The memory array of  claim 1 , wherein the charge trapping structure includes a charge trapping layer. 
     
     
       7. The memory array of  claim 6 , wherein the material of the charge trapping layer includes a silicon nitride. 
     
     
       8. The memory array of  claim 1 , wherein a first conductive type of the bit lines is different from a second conductive type of the trench channels.