Semiconductor integrated circuit device and delay fault testing method thereof

Abstract

A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

1. A semiconductor integrated circuit device, comprising:
 a first clock domain in which a plurality of first flip-flops are provided on a data path, and which is configured to operate with a first clock; 
 a second clock domain in which a plurality of second flip-flops are provided on a data path, and which is configured to operate with a second clock of a lower frequency than a frequency of the first clock; 
 a first test clock supplying section configured to supply a test clock based on the first clock to all of the first flip-flops at a time of a delay fault test; and 
 a second test clock supplying section configured to supply, at the time of the delay fault test, a test clock based on the first clock to a third flip-flop to which data from the first clock domain is input among the plurality of second flip-flops, and not to supply the test clock to a plurality of fourth flip-flops excluding the third flip-flop among the plurality of second flip-flops. 
 
     
     
       2. The semiconductor integrated circuit device according to  claim 1 , wherein the first and second flip-flops comprise a scan chain. 
     
     
       3. The semiconductor integrated circuit device according to  claim 1 , further comprising a logic circuit configured to perform a logical operation with respect to data that is supplied from the first flip-flop via the data path, and supply a result of the logical operation to the third flip-flop via the data path. 
     
     
       4. The semiconductor integrated circuit device according to  claim 1 , wherein the test clock comprises a launch pulse and a capture pulse that are generated at the same frequency as the frequency of the first clock. 
     
     
       5. The semiconductor integrated circuit device according to  claim 1 , wherein the first and second test clock supplying sections are configured to supply a third clock of a frequency that is less than or equal to a frequency of the second clock to all of the first and second flip-flops in a transfer period of the delay fault test, and to supply the test clock to all of the first and third flip-flops in a transition period of the delay fault test. 
     
     
       6. The semiconductor integrated circuit device according to  claim 5 , wherein the second test clock supplying section comprises:
 a first clock path configured to supply the test clock to the third flip-flop; 
 a second clock path configured to supply the test clock to all of the fourth flip-flops; and 
 a first gate circuit configured to cut-off the second clock path in the transition period. 
 
     
     
       7. The semiconductor integrated circuit device according to  claim 6 , wherein the first gate circuit is controlled by a control signal that indicates a transition period of the delay fault test and a period other than the transition period. 
     
     
       8. The semiconductor integrated circuit device according to  claim 5 , wherein the second test clock supplying section comprises:
 a first clock path configured to supply the test clock to the third flip-flop; 
 a reset path configured to supply a reset signal to all of the fourth flip-flops; and 
 a second gate circuit configured to allow the reset signal to pass through the reset path only in the transition period. 
 
     
     
       9. The semiconductor integrated circuit device according to  claim 8 , wherein the second gate circuit is controlled by a control signal that indicates a transition period of the delay fault test and a period other than the transition period. 
     
     
       10. The semiconductor integrated circuit device according to  claim 1 , comprising:
 a PLL circuit configured to generate the first clock; and 
 a clock division circuit configured to divide the first clock to generate the second clock. 
 
     
     
       11. The semiconductor integrated circuit device according to  claim 10 , comprising:
 a pulse control section configured to generate the test clock using the first clock from the PLL circuit. 
 
     
     
       12. The semiconductor integrated circuit device according to  claim 11 , comprising:
 a first selector configured to selectively provide an output of the PLL circuit and the test clock or the third clock to the first clock domain according to a mode signal that indicates the delay fault test period; and 
 a second selector configured to selectively provide an output of the clock division circuit and the test clock or the third clock to the second clock domain according to the mode signal. 
 
     
     
       13. The semiconductor integrated circuit device according to  claim 12 , comprising:
 a third selector configured to selectively provide an output of the pulse control section and the third clock to the first selector according to a control signal that indicates a transition period of the delay fault test and a period other than the transition period; and 
 a fourth selector configured to selectively provide an output of the pulse control section and the third clock to the second selector according to a control signal that indicates a transition period of the delay fault test and a period other than the transition period. 
 
     
     
       14. A delay fault testing method of a semiconductor integrated circuit device comprising a first clock domain in which a plurality of first flip-flops are provided on a data path and which is configured to operate with a first clock, and a second clock domain in which a plurality of second flip-flops are provided on a data path and which is configured to operate with a second clock of a lower frequency than a frequency of the first clock, in which the plurality of second flip-flops have a third flip-flop into which data from the first clock domain is input and a plurality of fourth flip-flops other than the third flip-flop among the plurality of second flip-flops, the method comprising:
 in a transfer period of the delay fault test, supplying a third clock of a frequency that is less than or equal to a frequency of the second clock to all of the first and second flip-flops; and 
 in a transition period of the delay fault test, supplying a test clock based on the first clock to all of the flip-flops excluding the fourth flip-flops among the first and second flip-flops. 
 
     
     
       15. The delay fault testing method according to  claim 14 , wherein:
 the first and second flip-flops comprise a scan chain; 
 in the transfer period, a value on the data path is set via the scan chain by supplying the third clock to all of the first and second flip-flops; 
 in the transition period, a value on the data path is caused to undergo a transition by supplying the test clock to all flip-flops excluding the fourth flip-flops among the first and second flip-flops; and 
 in the transfer period, the third clock is supplied to all of the first and second flip-flops to retrieve a value that has undergone a transition on the data path via the scan chain. 
 
     
     
       16. The delay fault testing method according to  claim 14 ,
 wherein the test clock comprises a launch pulse and a capture pulse that are generated at the same frequency as the frequency of the first clock. 
 
     
     
       17. The delay fault testing method according to  claim 14 , further comprising:
 in an other transfer period that is different from the transfer period, setting a value on the data path via the scan chain by supplying the third clock to all of the first and second flip-flops; and 
 in an other transition period that is different from the transition period, supplying a test clock based on the second clock to all of the first and second flip-flops.