ESD power clamp for high-voltage applications

Abstract

An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.

1. An electrostatic discharge (ESD) clamp comprising:
 a first power supply node; 
 an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; 
 a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node, with the second power supply voltage being lower than a first power supply voltage on the first power supply node, wherein the ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event; and 
 a low-voltage (LV) ESD clamp coupled to the second power supply node, wherein the LV ESD clamp comprises LV devices with maximum endurable voltages lower than the first power supply voltage. 
 
     
     
       2. The ESD clamp of  claim 1  further comprising a VSS node, wherein each of the ESD detection circuit and the bias circuit is coupled between the first power supply node and the VSS node, and wherein the LV ESD clamp is coupled between the second power supply node and the VSS node. 
     
     
       3. The ESD clamp of  claim 1 , wherein the ESD detection circuit comprises:
 a first resistor coupled between the first power supply node and a VSS node; 
 a first capacitor coupled between the first resistor and the VSS node; 
 a second capacitor coupled between the first power supply node and the VSS node; and 
 a second resistor coupled between the second capacitor and the VSS node. 
 
     
     
       4. The ESD clamp of  claim 3 , wherein the bias circuit comprises:
 a first PMOS transistor comprising a gate coupled to a node between the first resistor and the first capacitor; 
 a second PMOS transistor comprising a gate coupled to a node between the second resistor and the second capacitor, wherein source-to-drain paths of the first and the second PMOS transistors are coupled in series; and 
 a diode coupled in series with the source-to-drain paths of the first and the second PMOS transistors. 
 
     
     
       5. The ESD clamp of  claim 4  further comprising:
 an NMOS transistor comprising a drain coupled to the first power supply node, a gate coupled to a node between the source-to-drain paths of the first and the second PMOS transistors, and a source coupled to the second power supply node; 
 a third resistor coupled between the first power supply node and the gate of the NMOS transistor; and 
 a third capacitor coupled between the second power supply node and the VSS node. 
 
     
     
       6. An electrostatic discharge (ESD) clamp comprising:
 a first power supply node; 
 an ESD detection circuit coupled between the first power supply node and an electrical ground, wherein the ESD detection circuit is configured to detect an ESD transient on nodes of the ESD clamp; 
 a bias circuit coupled between the first power supply node and the electrical ground, wherein the bias circuit is configured to receive a signal from the ESD detection circuit, and output a voltage in response to the signal, with the voltage being applied to a second power supply node, and wherein the bias circuit comprises high-voltage (HV) devices; and 
 a low-voltage (LV) ESD clamp comprising a first end coupled to the second power supply node, and a second end coupled to the electrical ground, wherein the LV ESD clamp comprises LV devices with maximum endurable voltages lower than maximum endurable voltages of the HV devices. 
 
     
     
       7. The ESD clamp of  claim 6 , wherein the voltage outputted by the bias circuit is lower than a voltage on the first power supply node, and wherein the bias circuit is configured to keep the voltage substantially stable in response to a change in the voltage on the first power supply node with no ESD transient occurring on any node of the ESD clamp. 
     
     
       8. The ESD clamp of  claim 6 , wherein the maximum endurable voltages of the LV devices in the LV ESD clamp are lower than the voltage on the first power supply node. 
     
     
       9. The ESD clamp of  claim 6 , wherein the ESD detection circuit comprises:
 a first resistor coupled between the first power supply node and the electrical ground; 
 a first capacitor coupled between the first resistor and the electrical ground; 
 a second capacitor coupled between the first power supply node and the electrical ground; and 
 a second resistor coupled between the second capacitor and the electrical ground. 
 
     
     
       10. The ESD clamp of  claim 9 , wherein the bias circuit comprises:
 a first PMOS transistor comprising a gate coupled to a node between the first resistor and the first capacitor; 
 a second PMOS transistor comprising a gate coupled to a node between the second resistor and the second capacitor, wherein source-to-drain paths of the first and the second PMOS transistors are coupled in series; and 
 a diode coupled in series with the source-to-drain paths of the first and the second PMOS transistors. 
 
     
     
       11. The ESD clamp of  claim 10  further comprising:
 an NMOS transistor comprising a drain coupled to the first power supply node, a gate coupled to a node between the source-to-drain paths of the first and the second PMOS transistors, and a source coupled to the second power supply node; 
 a third resistor coupled between the first power supply node and the gate of the NMOS transistor; and 
 a third capacitor coupled between the second power supply node and the electrical ground. 
 
     
     
       12. An electrostatic discharge (ESD) clamp comprising:
 a power supply node; 
 an electrical ground; 
 an ESD detection circuit comprising:
 a first resistor coupled between the power supply node and the electrical ground; 
 a first capacitor coupled between the first resistor and the electrical ground; 
 a second capacitor coupled between the power supply node and the electrical ground; and 
 a second resistor coupled between the second capacitor and the electrical ground; 
 
 a bias circuit comprising:
 a first input coupled to a node between the first resistor and the first capacitor; 
 a second input coupled to a node between the second resistor and the second capacitor; and 
 an output; and 
 
 a low-voltage (LV) ESD clamp coupled between the output of the bias circuit and the electrical ground. 
 
     
     
       13. The ESD clamp of  claim 12 , wherein the LV ESD clamp comprises LV devices with maximum endurable voltages lower than a voltage on the power supply node. 
     
     
       14. The ESD clamp of  claim 12 , wherein the bias circuit comprises:
 a first PMOS transistor comprising a gate coupled the first input of the bias circuit; 
 a second PMOS transistor comprising a gate coupled to the second input of the bias circuit, wherein source-to-drain paths of the first and the second PMOS transistors are coupled in series; 
 a diode coupled in series with the source-to-drain paths of the first and the second PMOS transistors; and 
 an NMOS transistor comprising a drain coupled to the power supply node, a gate coupled to drains of the first and the second PMOS transistors, and a source coupled to the output of the bias circuit. 
 
     
     
       15. The ESD clamp of  claim 14 , wherein the bias circuit further comprises:
 a third resistor coupled between the power supply node and the gate of the NMOS transistor; and 
 a third capacitor coupled between the output of the bias circuit and the electrical ground. 
 
     
     
       16. The ESD clamp of  claim 14 , wherein the first and the second PMOS transistors and the NMOS transistor are high-voltage transistors.