Hardware accelerated reconfigurable processor for accelerating database operations and queries

Abstract

Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

1. A dataflow architecture hardware accelerator for assisting in processing queries from a host system to a database, wherein the hardware accelerator comprises dataflow architecture hardware processing elements configured to execute database machine code instructions for database query tasks in the dataflow architecture hardware processing elements from a database management system, said hardware accelerator comprising:
 a scanning processing element comprising dataflow architecture hardware configured to perform at least one of parallel field extraction and comparison of database columns based on executing at least one database machine code instruction on a data dataflow from the database; 
 an indexing processing element comprising dataflow architecture hardware configured to perform at least one database projection operation based on executing at least one database machine code instruction on a data dataflow from the database; and 
 an associative processing element comprising dataflow architecture hardware configured to perform at least one of grouping/aggregating, sieving, sorting, and an associative join based executing on at least one database machine code instruction on a data dataflow from the database. 
 
     
     
       2. The hardware accelerator according to  claim 1 , further comprising a dedicated memory that is capable of storing gigabyte portions of the database. 
     
     
       3. The hardware accelerator of  claim 2 , wherein the dedicated memory is at least 32 Gigabytes. 
     
     
       4. The hardware accelerator of  claim 2 , wherein the dedicated memory is at least 256 Gigabytes. 
     
     
       5. The hardware accelerator of  claim 2 , wherein the hardware accelerator is configured as a memory module package. 
     
     
       6. The hardware accelerator of  claim 2 , wherein the hardware accelerator is configured as a rack-mountable unit. 
     
     
       7. The hardware accelerator according to  claim 1 , wherein the hardware accelerator is coupled to the host system over a Peripheral Component Interconnect Express connection. 
     
     
       8. The hardware accelerator according to  claim 1 , wherein the hardware accelerator is coupled to the host system over a HyperTransport connection. 
     
     
       9. The hardware accelerator according to  claim 1 , wherein the hardware accelerator comprises field programmable gate array (FPGA) logic that reconfigures operations of at least one of the scanning processing element, the indexing processing element, and the associative processing element. 
     
     
       10. The hardware accelerator according to  claim 1 , wherein comprises Application Specific Integrated Circuit (ASIC) logic that reconfigures operations of at least one of the scanning processing element, the indexing processing element, and the associative processing element. 
     
     
       11. The hardware accelerator of  claim 1 , further comprising a task processor configured to assign the database query tasks from the host database system to at least one of the scanning processing element, the indexing processing element, and the associative processing element. 
     
     
       12. A database dataflow architecture hardware accelerator node coupled to a host system, wherein the dataflow architecture hardware accelerator executes database machine code instructions for database query tasks in hardware processing elements from a database management system running on the host system, said hardware accelerator comprising:
 a set of processing cores comprising combined dataflow architecture hardware logic for a scanning processing element to perform at least one of parallel field extraction and comparison of database columns based on executing at least one database machine code instruction on a data dataflow from the database, and an indexing processing element to perform at least one database projection operation, and a hardware-accelerated index content addressable memory processing element to perform at least one of grouping/aggregating, sieving, sorting, and an associative join based on executing at least one database machine code instruction on a data dataflow from the database; 
 a self routing switching fabric that couples the processing cores together; and 
 a memory capable of storing gigabyte portions of the database. 
 
     
     
       13. The hardware accelerator according to  claim 12 , further comprising a Peripheral Component Interconnect Express interface. 
     
     
       14. The hardware accelerator according to  claim 12 , further comprising a HyperTransport interface. 
     
     
       15. The hardware accelerator according to  claim 12 , wherein the set of processing cores are implemented based on field programmable gate arrays. 
     
     
       16. The hardware accelerator according to  claim 12 , wherein the set of processing cores are implemented based on Application Specific Integrated Circuits. 
     
     
       17. The hardware accelerator according  claim 12 , wherein the hardware accelerator comprises a set of four identical processing cores. 
     
     
       18. The hardware accelerator according  claim 12 , wherein the hardware accelerator comprises pairs of identical processing cores. 
     
     
       19. The hardware accelerator according to  claim 12 , wherein the memory is at least 256 Gigabytes. 
     
     
       20. The hardware accelerator according to  claim 12 , wherein the memory is at least 32 Gigabytes. 
     
     
       21. The hardware accelerator according to  claim 12 , wherein the memory is at least 16 Gigabytes. 
     
     
       22. The hardware accelerator according to  claim 12 , wherein the set of processing cores are programmable by database machine code instructions. 
     
     
       23. The hardware accelerator according to  claim 12 , wherein the set of processing cores are reconfigurable in the manner in which they execute database machine code instructions.