Semiconductor device provided with tin diffusion inhibiting layer, and manufacturing method of the same

Abstract

A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.

1. A semiconductor device comprising:
 a semiconductor substrate; 
 a connection pad provided on the semiconductor substrate; 
 a wiring line connected with the connection pad; 
 a tin diffusion inhibiting layer provided above the wiring line and includes a solder; and 
 a solder bump provided on the tin diffusion inhibiting layer, 
 wherein the melting point of the tin diffusion inhibiting layer is higher than the melting point of the solder bump. 
 
     
     
       2. The semiconductor device according to  claim 1 , further the wiring line comprising an overcoat film which is provided on an insulating film and which comprises an opening corresponding to a land of the wiring line. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the tin diffusion inhibiting layer is formed by heating at 180° C. or more and 280° C. or less and is not remelted at 180° C. or more and 280° C. or less. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the tin diffusion inhibiting layer is a melting point rising type solder. 
     
     
       5. The semiconductor device according to  claim 4 , wherein the melting point rising type solder includes a tin-copper-based lead-free solder having a noneutectic composition. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the tin diffusion inhibiting layer includes a layer in which copper particles are dispersed into a thermosetting resin. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the solder bump includes a melting point non-rising type solder. 
     
     
       8. The semiconductor device according to  claim 7 , wherein the melting point non-rising type solder includes a tin-silver-based lead-free solder having a eutectic composition. 
     
     
       9. The semiconductor device according to  claim 1 , wherein a copper layer is provided under the tin diffusion inhibiting layer on the land of the wiring line.