Dynamic random access memory cell including an asymmetric transistor and a columnar capacitor

Abstract

A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

1. A semiconductor structure comprising:
 a field effect transistor located on a semiconductor fin that is located on a substrate; 
 a semiconductor column of integral construction with said semiconductor fin; 
 an inner electrode comprising a doped semiconductor material and located in said semiconductor column; 
 a dielectric layer of unitary construction located on said semiconductor fin and said semiconductor column; 
 an outer electrode located directly on said dielectric layer and overlying said semiconductor column; and 
 a gate electrode located directly on said dielectric layer and overlying a middle portion of said semiconductor fin. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein a topmost surface of said semiconductor fin is coplanar with a topmost surface of said semiconductor column. 
     
     
       3. The semiconductor structure of  claim 1 , wherein said semiconductor fin and said semiconductor column comprise a same semiconductor material, are single crystalline, and are epitaxially aligned to each other. 
     
     
       4. The semiconductor structure of  claim 1 , wherein said semiconductor fin includes:
 a body region having a doping of a first conductivity type; 
 a source region abutting said body region and said inner electrode and having a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type; and 
 a drain region abutting said body region and having a doping of said second conductivity type. 
 
     
     
       5. The semiconductor structure of  claim 4 , wherein said semiconductor fin further comprises a halo region abutting said body region and said drain region and having of doping of said first conductivity type at a greater dopant concentration than said body region. 
     
     
       6. The semiconductor structure of  claim 4 , wherein each of said source region, said drain region, and said body region abuts a pair of sidewalls of said semiconductor fin. 
     
     
       7. The semiconductor structure of  claim 4 , wherein said dielectric layer, said body region, and said inner electrode encapsulates said source region. 
     
     
       8. The semiconductor structure of  claim 1 , wherein said outer electrode and said gate electrode comprise a same conductive material, and wherein a topmost surface of said gate electrode is substantially coplanar with a topmost surface of said outer electrode. 
     
     
       9. The semiconductor structure of  claim 1 , further comprising a dielectric spacer layer laterally abutting said drain region, said gate electrode, and said outer electrode. 
     
     
       10. The semiconductor structure of  claim 9 , further comprising:
 a drain-side metal semiconductor alloy region vertically abutting said drain region; 
 a first gate-side metal semiconductor alloy region vertically abutting a first portion of said gate electrode located above said semiconductor fin; and 
 a second gate-side metal semiconductor alloy region vertically abutting a second portion of said gate electrode, laterally abutting said dielectric spacer, and not abutting said first gate-side metal semiconductor alloy region. 
 
     
     
       11. The semiconductor structure of  claim 9 , further comprising:
 a first outer-electrode-side metal semiconductor alloy region vertically abutting a first portion of said outer electrode located above said semiconductor column; and 
 a second outer-electrode-side metal semiconductor alloy region vertically abutting a second portion of said outer electrode and laterally abutting said dielectric spacer. 
 
     
     
       12. The semiconductor structure of  claim 1 , further comprising an insulator layer located in said substrate and vertically abutting said semiconductor fin and said semiconductor column. 
     
     
       13. The semiconductor structure of  claim 1 , further comprising:
 a semiconductor layer located in said substrate vertically abutting said semiconductor fin and said semiconductor column, wherein said semiconductor layer is epitaxially aligned to said semiconductor fin and said semiconductor column; and 
 a doped semiconductor portion located in said semiconductor layer and abutting said inner electrode. 
 
     
     
       14. The semiconductor structure of  claim 1 , wherein said semiconductor column includes:
 an inner sidewall directly adjoined to an inner periphery of a top surface of said semiconductor column; and 
 an outer sidewall directly adjoined to an outer periphery of said top surface of said semiconductor column. 
 
     
     
       15. A method of forming a semiconductor structure comprising:
 forming a semiconductor fin and a semiconductor column directly on a substrate, wherein said semiconductor column is of integral construction with said semiconductor fin; 
 forming an inner electrode in said semiconductor column; 
 forming a dielectric layer and a conductive layer on said semiconductor fin and said semiconductor column; and 
 forming a field effect transistor and a capacitor, wherein said capacitor comprises said inner electrode, a first portion of said dielectric layer, and an outer electrode formed on said dielectric layer, wherein said outer electrode and a gate electrode of said field effect transistor are formed by patterning said conductive layer, and wherein a second portion of said dielectric layer is a gate dielectric of said field effect transistor. 
 
     
     
       16. The method of  claim 15 , wherein said first portion of said dielectric layer and said second portion of said dielectric layer are of integral and unitary construction. 
     
     
       17. The method of  claim 15 , wherein further comprising:
 patterning a semiconductor material layer having a doping of a first conductivity type to form said semiconductor fin and said semiconductor column; and 
 implanting dopants of a second conductivity into said semiconductor column and a first end of said semiconductor fin abutting said semiconductor column, wherein a middle portion and a second end of said semiconductor fin are masked by a masking layer. 
 
     
     
       18. The method of  claim 17 , further comprising:
 forming a source region in a sub-portion of said middle portion of semiconductor fin by implanting dopants of said second conductivity type through a portion of said dielectric layer between said gate electrode and said outer electrode; and 
 forming a drain region in said second end of said semiconductor fin by implanting dopants of said second conductivity type into said second end of said semiconductor fin. 
 
     
     
       19. The method of  claim 18 , further comprising:
 forming a masking layer having an edge over said gate electrode and covering said sub-portion of said middle portion of semiconductor fin, said first end of said semiconductor fin, and said semiconductor column; and 
 removing said dielectric layer from above said second end of said semiconductor fin employing said masking layer as an etch mask. 
 
     
     
       20. The method of  claim 18 , further comprising forming a halo region in said semiconductor fin, wherein said halo region abuts a body region having a doping of said first conductivity type and said drain region, and wherein said halo region has a doping of said first conductivity type and has a greater dopant concentration than said body region.