Memory emulation using resistivity-sensitive memory

Abstract

Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.

1. A system including embedded non-Flash re-writeable two-terminal non-volatile memory, comprising:
 a silicon substrate including active circuitry fabricated on a logic plane; 
 at least one memory plane fabricated directly over the silicon substrate and in direct contact with the silicon substrate such that the at least one memory plane is positioned directly over the logic plane; 
 a non-volatile two-terminal cross-point memory array embedded in the memory plane and including a plurality of first and second conductive array lines that are electrically coupled with a portion of the active circuitry, the non-volatile two-terminal cross-point memory array including a plurality of two-terminal non-volatile memory elements, each memory element is positioned between a cross-point of a unique pair of first and second conductive array lines and is directly electrically in series with its unique pair of first and second conductive array lines, each two-terminal non-volatile memory element is operative to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across its two terminals, the data is retained in the absence of electrical power, the data is written by applying a write voltage across its two terminals without performing a prior erase operation, and the read voltage is less than the write voltage; and 
 a control unit included in the active circuitry and in electrical communication with the non-volatile two-terminal cross-point memory array, data operations on the non-volatile two-terminal cross-point memory array are executed exclusively by the control unit, and the non-volatile two-terminal cross-point memory array is used exclusively by the control unit for data storage purposes. 
 
     
     
       2. The system of  claim 1 , wherein the non-volatile two-terminal cross-point memory array replaces Flash memory and circuitry included in the control unit emulates Flash memory data operations on the non-volatile two-terminal cross-point memory array. 
     
     
       3. The system of  claim 1 , wherein the data stored in the non-volatile two-terminal cross-point memory array comprises data for system boot of the control unit. 
     
     
       4. The system of  claim 1 , wherein the control unit is an electrical device selected from the group consisting of a microprocessor (μP), a micro controller, a computer, and a digital signal processor (DSP). 
     
     
       5. The system of  claim 1 , wherein the data operations on the non-volatile two-terminal cross-point memory array comprise only read operations. 
     
     
       6. The system of  claim 1 , wherein the data operations on the non-volatile two-terminal cross-point memory array comprise read and write operations. 
     
     
       7. The system of  claim 1 , wherein the data operations on the non-volatile two-terminal cross-point memory array comprise write operations. 
     
     
       8. The system of  claim 7 , wherein the write operation on the non-volatile two-terminal cross-point memory array does not require a prior Flash erase operation on the non-volatile two-terminal cross-point memory array. 
     
     
       9. The system of  claim 8 , wherein a first cycle time for the write operation is shorter in duration than a second cycle time for a conventional Flash memory write operation. 
     
     
       10. The system of  claim 1  and further comprising:
 a logic block included in the active circuitry and in electrical communication with the control unit; and 
 an input/output (I/O) unit included in the active circuitry and in electrical communication with the control unit and the logic block, the I/O unit configured for electrical communication with an external system. 
 
     
     
       11. The system of  claim 1  and further comprising:
 an interconnect structure fabricated on the logic plane and operative to electrically couple the first and second conductive array lines with the portion of the active circuitry, the at least one memory plane in contact with and fabricated directly above the interconnect structure. 
 
     
     
       12. The system of  claim 1  and further comprising:
 a plurality of the memory planes that are in contact with one another and vertically stacked upon one another; and 
 a plurality of additional non-volatile two-terminal cross-point memory arrays embedded in and distributed among the plurality of the memory planes, each additional non-volatile two-terminal cross-point memory array including another plurality of the two-terminal memory elements and first and second conductive array lines electrically coupled with another portion of the active circuitry. 
 
     
     
       13. The system of  claim 12 , wherein at least one of the memory planes includes a plurality of the additional non-volatile two-terminal cross-point memory arrays and the plurality of the additional non-volatile two-terminal cross-point memory arrays are horizontally configured in their respective memory plane. 
     
     
       14. The system of  claim 1  and further comprising:
 a memory controller included in the active circuitry; 
 a logic block included in the active circuitry and in electrical communication with the control unit; and 
 an input/output (I/O) unit included in the active circuitry and in electrical communication with the control unit and the logic block, the I/O unit configured for electrical communication with an external system; 
 a data bus and an address bus fabricated in the logic plane and electrically coupled with the control unit, the memory controller, and the I/O unit; and 
 a plurality of the memory planes that are in contact with one another and vertically stacked upon one another, a bottommost of the memory planes in contact with the silicon substrate, each memory plane including at least one additional non-volatile two-terminal cross-point memory array embedded therein, each additional non-volatile two-terminal cross-point memory array including first and second conductive array lines electrically coupled with another portion of the active circuitry and another plurality of two-terminal memory elements. 
 
     
     
       15. The system of  claim 14  and further comprising:
 an interconnect structure fabricated on the logic plane and operative to electrically couple all of the first and second conductive array lines with their respective portions of the active circuitry, the bottommost memory plane is in contact with and is fabricated directly above the interconnect structure. 
 
     
     
       16. The system of  claim 14 , wherein the non-volatile two-terminal cross-point memory array that is in electrical communication with the control unit is also in electrical communication with the address bus and the data bus. 
     
     
       17. The system of  claim 14 , wherein at least one of the plurality of the additional non-volatile two-terminal cross-point memory arrays is in electrical communication with the memory controller, the address bus, and the data bus. 
     
     
       18. The system of  claim 14 , wherein at least one of the plurality of the additional non-volatile two-terminal cross-point memory arrays is in electrical communication with the address bus and the data bus. 
     
     
       19. The system of  claim 14 , wherein at least one of the memory planes includes a plurality of the additional non-volatile two-terminal cross-point memory arrays and the plurality of the additional non-volatile two-terminal cross-point memory arrays are horizontally configured in their respective memory plane. 
     
     
       20. The system of  claim 1 , wherein each two-terminal non-volatile memory element includes an electrolytic tunnel barrier having a thickness less than 50 Angstroms and in contact with a conductive metal oxide including mobile oxygen ions.