Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

1. A method of manufacturing a semiconductor device comprising a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode, comprising:
 stacking a bottom electrode layer, a dielectric layer and an top electrode layer; 
 patterning said top electrode layer to form a plurality of top electrodes arranged in a column; 
 forming a mask pattern that covers said plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of said plurality of top electrodes exposed; and 
 patterning said dielectric layer using said mask pattern. 
 
     
     
       2. The method of manufacturing a semiconductor device according to  claim 1 , further comprising:
 forming an interlayer film on said plurality of capacitors; and 
 forming a via hole in said interlayer film on said outermost top electrode. 
 
     
     
       3. The method of manufacturing a semiconductor device according to  claim 1 , further comprising:
 forming an interlayer film on said plurality of capacitors; and 
 forming a plurality of via holes that extend to said plurality of top electrodes except said outermost top electrode in said interlayer film. 
 
     
     
       4. The method of manufacturing a semiconductor device according to  claim 1 , further comprising:
 patterning said bottom electrode layer to form a plurality of bottom electrodes; 
 forming an interlayer film on said plurality of capacitors; and 
 forming a via hole that extends to the bottom electrode in said interlayer film on said bottom electrode. 
 
     
     
       5. The method of manufacturing a semiconductor device according to  claim 1 , wherein a bottom electrode is formed of a single layer film or a multilayer film of one or more conductors selected from the group consisting of Ir, IrOx, Pt, SRO, LNO, LSCO, Ru, RuO2 and SrRuO3. 
     
     
       6. The method of manufacturing a semiconductor device according to  claim 1 , wherein the bottom electrode layer, the dielectric layer and the top electrode layer are patterned by using inductively coupled plasma. 
     
     
       7. The method of manufacturing a semiconductor device according to  claim 1 , wherein the bottom electrode layer, the dielectric layer and the top electrode layer are patterned by using a chlorine-based etching gas. 
     
     
       8. A method of manufacturing a semiconductor device comprising a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode, comprising:
 stacking a bottom electrode layer, a dielectric layer and an top electrode layer; 
 patterning said top electrode layer to form a plurality of top electrodes arranged in a column; 
 forming a mask for a bottom electrode including a first mask that covers a first top electrode located at the outermost end of said plurality of top electrodes and a second mask that is separated from said first mask and covers a plurality of second top electrodes, which are said plurality of top electrodes excluding said first top electrodes; and 
 patterning said bottom electrode layer using said bottom electrode mask to form said bottom electrode.