Three dimensional semiconductor memory device and method of fabricating the same

Abstract

Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

1. A method of forming a nonvolatile memory device, comprising:
 forming an electrically insulating layer comprising a composite of a sacrificial layer having upper and lower surfaces and first and second mold layers directly on the upper and lower surfaces, respectively, on a substrate; 
 forming an opening extending through the electrically insulating layer, said opening exposing inner sidewalls of the first and second mold layers and the sacrificial layer; 
 lining a sidewall of the opening with an electrically insulating protective layer; 
 forming a first semiconductor layer on an inner sidewall of the electrically insulating protective layer within the opening; 
 selectively etching at least a portion of the sacrificial layer from between the first and second mold layers to define a recess therein that exposes an outer sidewall of the electrically insulating protective layer; 
 selectively etching the exposed outer sidewall of the electrically insulating protective layer to expose a portion of the first semiconductor layer; 
 forming a gate dielectric layer on the exposed portion of the first semiconductor layer in the recess; and 
 forming a gate electrode on the gate dielectric layer. 
 
     
     
       2. The method of  claim 1 , wherein said forming a gate dielectric layer comprises forming a composite of a tunnel insulating layer, a charge storage layer and an electrically insulating blocking layer on the exposed portion of the first semiconductor layer in the recess. 
     
     
       3. The method of  claim 2 , wherein said forming a gate dielectric layer comprises lining the exposed portion of the first semiconductor layer in the recess and exposed portions of the first and second mold layers in the recess with the tunnel insulating layer. 
     
     
       4. The method of  claim 1 , wherein said forming a first semiconductor layer is followed by filling the opening with an electrically insulating gap filling region. 
     
     
       5. The method of  claim 1 , wherein said forming an opening is preceded by forming a capping mask pattern on the first mold layer; and wherein said forming an opening comprises selectively etching an opening that extends through the electrically insulating layer and defines a recess hole in the substrate, using the capping mask pattern as an etching mask. 
     
     
       6. The method of  claim 5 , further comprising laterally recessing the exposed inner sidewalls of the first and second mold layers and the sacrificial layer in the opening, using the capping mask pattern as an etching mask. 
     
     
       7. The method of  claim 6 , wherein said lining the sidewall of the opening with an electrically insulating protective layer comprises lining the recess hole and the recessed inner sidewalls of the first and second mold layers and the sacrificial layer with the electrically insulating protective layer. 
     
     
       8. The method of  claim 7 , wherein said forming a semiconductor layer on an inner sidewall of the electrically insulating protective layer is preceded by selectively removing the electrically insulating protective layer from the recess hole in the substrate. 
     
     
       9. The method of  claim 8 , wherein said selectively removing the electrically insulating protective layer from the recess hole is preceded by selectively implanting etch-enhancing impurities into a portion of the electrically insulating protective layer in the recess hole, using the capping mask pattern as an implant mask. 
     
     
       10. The method of  claim 9 , wherein said forming a semiconductor layer on an inner sidewall of the electrically insulating protective layer comprises depositing the semiconductor layer into the recess hole. 
     
     
       11. The method of  claim 8 , wherein said forming a semiconductor layer on an inner sidewall of the electrically insulating protective layer comprises depositing the semiconductor layer into the recess hole. 
     
     
       12. The method of  claim 6 , wherein said forming a semiconductor layer on an inner sidewall of the electrically insulating protective layer comprises depositing the semiconductor layer into the recess hole. 
     
     
       13. The method of  claim 11 , wherein said depositing the semiconductor layer into the recess hole is followed by filling the opening with an electrically insulating gap filling region. 
     
     
       14. A method of forming a nonvolatile memory device, comprising:
 forming a vertical stack of a plurality of sacrificial layers and a plurality of electrically insulating mold layers arranged in an alternating sequence, on a substrate; 
 selectively etching through the vertical stack to define an opening therein that exposes the substrate and recesses inner sidewalls of the plurality of sacrificial layers relative to inner sidewalls of the plurality of mold layers; 
 lining the recessed inner sidewalls of the plurality of sacrificial layers and the inner sidewalls of the plurality of mold layers with an electrically insulating protective layer; 
 selectively removing the protective layer from the inner sidewalls of the plurality of mold layers to define protective spacers on the recessed inner sidewalls of the plurality of sacrificial layers; 
 forming a semiconductor active layer on inner sidewalls of the protective spacers, the inner sidewalls of the plurality of mold layers and on the exposed substrate; 
 selectively removing portions of the plurality of sacrificial layers from the vertical stack to define recesses between the plurality of mold layers and expose the protective spacers within the recesses; and 
 forming gate electrodes on the exposed protective spacers. 
 
     
     
       15. The method of  claim 14 , wherein said forming gate electrodes comprises forming gate electrodes and gate dielectric layers on the exposed protective spacers. 
     
     
       16. A method of forming a nonvolatile memory device, comprising:
 forming an electrically insulating layer comprising a composite of a sacrificial layer having upper and lower surfaces and first and second mold layers directly on the upper and lower surfaces, respectively, on a substrate; 
 forming a capping mask pattern on the electrically insulating layer; 
 selectively etching an opening extending through the electrically insulating layer and into the substrate, using the capping mask pattern as an etching mask, said opening exposing inner sidewalls of the first and second mold layers and the sacrificial layer and a recess hole within the substrate; 
 recessing the exposed inner sidewalls of the first and second mold layers and the sacrificial layer relative to a sidewall of an opening in the capping mask pattern to thereby define an undercut region within the opening in the electrically insulating layer; 
 lining the recessed inner sidewalls of the first and second mold layers and the sacrificial layer in the undercut region with an electrically insulating protective layer; 
 thinning the electrically insulating protective layer on the recessed inner sidewalls of the first and second mold layers and the sacrificial layer; and then 
 forming a semiconductor layer on the electrically insulating protective layer. 
 
     
     
       17. The method of  claim 16 , wherein said lining the recessed inner sidewalls of the first and second mold layers and the sacrificial layer comprises lining the recess hole with the electrically insulating protective layer; and wherein said thinning the electrically insulating protective layer comprises selectively implanting dopants into a first portion of the electrically insulating protective layer within the recess hole and then etching the first portion of the electrically insulating protective layer at a faster rate relative to a second portion of the electrically insulating protective layer on the recessed inner sidewalls of the first and second mold layers and the sacrificial layer. 
     
     
       18. The method of  claim 17 , further comprising replacing the sacrificial layer with a gate electrode. 
     
     
       19. The method of  claim 18 , wherein said replacing comprises:
 removing the sacrificial layer to define a lateral recess extending between the first and second mold layers that exposes a portion of the electrically insulating protective layer; 
 removing the exposed portion of the electrically insulating protective layer to thereby expose a portion of the semiconductor layer; 
 forming a gate insulating layer comprising a composite of a tunnel oxide layer and a charge storage layer on the exposed portion of the semiconductor layer; and 
 forming the gate electrode on the gate insulating layer.