Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns

Abstract

A method of making a substrate for a semiconductor package includes providing a laminated layer structure including a backing layer and a metal layer attached to the backing layer. A circuit layer is plated atop a first surface of the metal layer to form a circuit-on-metal structure. The circuit-on-metal structure is coupled to a dielectric layer by causing the dielectric layer to flow around the circuit layer to the first surface of the metal layer so that the circuit layer is embedded within the dielectric layer and the first surface of the metal layer is in direct contact with a first surface of the dielectric layer. The backing layer is then removed completely. The metal layer is then removed completely.

1. A method of making a substrate for a semiconductor package, the method comprising:
 providing a laminated layer structure comprising:
 a backing layer; and 
 a metal layer attached to the backing layer; 
 
 plating a circuit layer atop a first surface of the metal layer to form a circuit-on-metal structure; 
 coupling the circuit-on-metal structure to a dielectric layer comprising causing the dielectric layer to flow around the circuit layer to the first surface of the metal layer so that the circuit layer is embedded within the dielectric layer and the first surface of the metal layer is in direct contact with a first surface of the dielectric layer; 
 removing the backing layer completely subsequent to the coupling the circuit-on-metal structure to a dielectric layer; and 
 removing the metal layer completely subsequent to the removing the backing layer. 
 
     
     
       2. The method of  claim 1  wherein the laminated layer structure further comprises:
 an organic releasing layer laminating the metal layer to the backing layer, 
 wherein the removing the backing layer comprises peeling the backing layer from the metal layer. 
 
     
     
       3. The method of  claim 2 , further comprising prior to the plating:
 applying a plating resist material to the first surface of the metal layer; and 
 laser-ablating the plating resist material to form a plating resist structure defining voids in a shape of the circuit layer. 
 
     
     
       4. The method of  claim 2 , further comprising prior to the plating:
 applying a photosensitive plating resist material to the first surface of the metal layer; 
 exposing the photosensitive plating resist material; and 
 removing regions of the photosensitive plating resist material to form a plating resist structure defining voids in a shape of the circuit layer. 
 
     
     
       5. The method of  claim 4 , wherein the exposing is performed by directing a laser beam along a surface of the photosensitive plating resist material to expose the photosensitive plating resist material. 
     
     
       6. The method of  claim 2 , wherein the metal layer has a thickness less than or equal to five microns. 
     
     
       7. The method of  claim 2 , wherein the metal layer has a thickness substantially equal to three microns. 
     
     
       8. The method of  claim 2 , wherein the backing layer is attached to a backing dielectric layer. 
     
     
       9. The method of  claim 8 , wherein the removing the backing layer further comprises:
 removing the backing dielectric layer, the backing layer and the organic releasing layer from the metal layer. 
 
     
     
       10. The method of  claim 8  wherein the peeling the backing layer from the metal layer further comprises peeling the backing dielectric layer and the organic releasing layer from the metal layer. 
     
     
       11. The method of  claim 2 , wherein the backing layer comprises copper. 
     
     
       12. The method of  claim 1  wherein the metal layer is a first metal layer, the circuit layer is a first circuit layer, and the circuit-on-metal structure is a first circuit-on-metal structure, the method further comprising:
 providing a second metal layer; 
 plating a second circuit layer atop a first surface of the second metal layer to form a second circuit-on-metal structure; and 
 bonding the second circuit-on-metal structure to a second surface of the dielectric layer so that the second circuit layer is embedded within the dielectric layer and the first surface of the second metal layer is in contact with the second surface of the dielectric layer. 
 
     
     
       13. The method of  claim 12  wherein the second circuit-on-metal structure is bonded to the second surface of the dielectric layer subsequent to the coupling the circuit-on-metal structure to a dielectric layer. 
     
     
       14. The method of  claim 12 , wherein the removing the metal layer is performed by etching. 
     
     
       15. The method of  claim 12 , wherein the removing the metal layer is performed by machining. 
     
     
       16. The method of  claim 12 , wherein the providing a laminated layer structure comprises providing the first metal layer attached to the backing layer by an organic releasing layer. 
     
     
       17. The method of  claim 16 , wherein the backing layer is attached to a backing dielectric layer, wherein the removing the backing layer comprises:
 removing the backing dielectric layer, the backing layer and the organic releasing layer from the first metal layer. 
 
     
     
       18. The method of  claim 1  further comprising:
 applying a resist material to the first surface of the metal layer; 
 patterning the resist material to form a patterned resist material defining circuit pattern regions, wherein the plating comprises plating the circuit layer within the circuit pattern regions atop the first surface of the metal layer; 
 removing the patterned resist material, 
 wherein the removing the metal layer comprises etch removing the metal layer. 
 
     
     
       19. The method of  claim 18  wherein the patterning the resist material comprises laser-ablating the resist material. 
     
     
       20. The method of  claim 18  wherein the resist material comprises a photosensitive resist material, the patterning the resist material comprising:
 exposing the photosensitive resist material; and 
 removing regions of the photosensitive resist material. 
 
     
     
       21. The method of  claim 20 , wherein the exposing is performed by directing a laser beam along a surface of the photosensitive resist material. 
     
     
       22. The method of  claim 1  wherein the laminated layer structure is a first laminated layer structure, the backing layer is a first backing layer, the metal layer is a first metal layer, the circuit layer is a first circuit layer, and the circuit-on-metal structure is a first circuit-on-metal structure, the method further comprising:
 providing a second laminated layer structure comprising:
 a second backing layer; and 
 a second metal layer attached to the second backing layer; 
 
 plating a second circuit layer atop a first surface of the second metal layer to form a second circuit-on-metal structure; 
 coupling the second circuit-on-metal structure to the dielectric layer so that the second circuit layer is embedded within the dielectric layer and the first surface of the second metal layer is in contact with a second surface of the dielectric layer; 
 removing the second backing layer; and 
 removing the second metal layer. 
 
     
     
       23. The method of  claim 22  further comprising electrically connecting the first circuit layer to the second circuit layer through the dielectric layer. 
     
     
       24. The method of  claim 22  further comprising:
 forming via holes in the dielectric layer between the first circuit layer and the second circuit layer; and 
 filling the via holes with an electrically conductive material to form vias electrically connecting the first circuit layer to the second circuit layer. 
 
     
     
       25. The method of  claim 24  wherein the via holes are formed by mechanical drilling. 
     
     
       26. The method of  claim 24  wherein the via holes extend through the first circuit layer to a bottom side of the second circuit layer. 
     
     
       27. The method of  claim 24  wherein the via holes extend though the first circuit layer and the second circuit layer. 
     
     
       28. The method of  claim 22  wherein the second circuit-on-metal structure is coupled to the second surface of the dielectric layer subsequent to the coupling of the first circuit-on-metal structure to the first surface of the dielectric layer. 
     
     
       29. The method of  claim 1  further comprising forming plated areas on the first circuit layer. 
     
     
       30. The method of  claim 1  further comprising forming plated areas on the second circuit layer. 
     
     
       31. The method of  claim 1  further comprising forming plated areas on the first and second circuit layers. 
     
     
       32. The method of  claim 2  wherein the laminated layer structure is a first laminated layer structure, the backing layer is a first backing layer, the organic releasing layer is a first organic releasing layer, the metal layer is a first metal layer, the circuit layer is a first circuit layer, and the circuit-on-metal structure is a first circuit-on-metal structure, the method further comprising:
 providing a second laminated layer structure comprising:
 a second backing layer; 
 a second organic releasing layer; and 
 a second metal layer laminated to the second backing layer by the second organic releasing layer; 
 
 plating a second circuit layer atop a first surface of the second metal layer to form a second circuit-on-metal structure; 
 bonding the second circuit-on-metal structure to the dielectric layer so that the second circuit layer is embedded within the dielectric layer and the first surface of the second metal layer is in contact with a second surface of the dielectric layer; 
 releasing the second metal layer from the second backing layer by peeling the second backing layer from the second metal layer; and 
 removing the second metal layer. 
 
     
     
       33. The method of  claim 32  wherein the second circuit-on-metal structure is bonded to the second surface of the dielectric layer subsequent to the bonding of the first circuit-on-metal structure to the first surface of the dielectric layer.