Phase change memory device capable of increasing sensing margin and method for manufacturing the same

Abstract

A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes.

What is claimed is: 
     
       1. A method for manufacturing a phase change memory device, comprising the steps of:
 forming a device isolation structure, which defines active regions, in a semiconductor substrate; 
 forming an N-type well in the semiconductor substrate; 
 forming a P-type well and a P-type ion-implantation layer in the N-type well, by implementing an impurity-ion implantation process for the semiconductor substrate; 
 forming line-shaped N-type impurity regions in surfaces of the active regions; 
 forming a plurality of vertical PN diodes on the N-type impurity regions; and 
 forming phase change memory cells on the vertical PN diodes. 
 
     
     
       2. The method according to  claim 1 , wherein the step of forming the P-type well and the P-type ion-implantation layer comprises the steps of:
 forming a P-type well in the semiconductor substrate at a position lower than the device isolation structure; and 
 forming a P-type ion-implantation layer in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate. 
 
     
     
       3. The method according to  claim 1 , wherein the step of forming the P-type well and the P-type ion-implantation layer comprises the steps of:
 forming a P-type ion-implantation layer in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; and 
 forming a P-type well in the semiconductor substrate at a position lower than the device isolation structure. 
 
     
     
       4. The method according to  claim 1 , wherein the N-type well is formed in the semiconductor substrate at a position lower than the P-type well. 
     
     
       5. The method according to  claim 1 , wherein the P-type well is formed through an ion-implantation process which is implemented with energy of 100˜500 KeV at a dose of 1×10 17 ˜1×10 19  ions/cm 3 . 
     
     
       6. The method according to  claim 1 , wherein the P-type ion-implantation layer is formed at a depth which is the same as or lower than the device isolation structure. 
     
     
       7. The method according to  claim 1 , wherein the P-type ion-implantation layer is formed through an ion-implantation process which is implemented with energy of 50˜200 KeV at a dose of 1×10 17 ˜1×10 19  ions/cm 3 . 
     
     
       8. The method according to  claim 1 , wherein, after the step of forming the P-type well and the P-type ion-implantation layer and before the step of forming the N-type impurity regions, the method further comprises the step of:
 forming a P-type ion-implantation layer for preventing the occurrence of a punch-through, in the semiconductor substrate at a depth similar to the N-type impurity regions. 
 
     
     
       9. The method according to  claim 8 , wherein the P-type ion-implantation layer for preventing the occurrence of a punch-through is formed at a depth which is the same as or lower than the N-type impurity regions. 
     
     
       10. The method according to  claim 8 , wherein the P-type ion-implantation layer for preventing the occurrence of a punch-through is formed through an ion-implantation process which is implemented with energy of 10˜150 KeV at a dose of 1×10 17 ˜1×10 19  ions/cm 3 . 
     
     
       11. The method according to  claim 1 , wherein the N-type impurity regions are formed through an ion-implantation process which is implemented with energy of 10˜80 KeV at a dose of 1×10 19 ˜1×10 21  ions/cm 3 . 
     
     
       12. The method according to  claim 1 , wherein, after the step of forming the phase change memory cells, the method further comprises the steps of:
 forming bit lines to come into contact with the phase change memory cells; 
 forming plugs on the N-type impurity regions; and 
 forming word lines over the bit lines to come into contact with the N-type impurity regions via the plugs.