Semiconductor devices including fin shaped semiconductor regions and stress inducing layers

Abstract

A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

What is claimed is: 
     
       1. A semiconductor device comprising;
 a substrate; 
 a fin shaped semiconductor region on the substrate, the fin shaped semiconductor region including a channel region and first and second junction regions on opposite sides of the channel region; 
 a gate electrode disposed over the fin shaped semiconductor region; and 
 a stress inducing layer formed between the gate electrode and the substrate. 
 
     
     
       2. A semiconductor device according to  claim 1 , wherein the stress inducing layer is formed along a surface of the fin shaped semiconductor region opposite the substrate. 
     
     
       3. A semiconductor device according to  claim 2  wherein the stress inducing layer comprises a continuous stress inducing layer of a same material that extends continuously between the gate electrode and the substrate and on the surface of the fin shaped semiconductor region opposite the substrate, so that portions of the fin shaped semiconductor region are between the stress inducing layer and the substrate, and so that portions of the stress inducing layer are between the gate electrode and the substrate. 
     
     
       4. A semiconductor device according to  claim 1 , wherein the stress inducing layer is formed along a sidewall of the fin shaped semiconductor region. 
     
     
       5. A semiconductor device according to  claim 1 , wherein the gate electrode extends across a surface of the fin shaped semiconductor region opposite the substrate and along a portion of a sidewall of the fin shaped semiconductor region. 
     
     
       6. A semiconductor device according to  claim 1 , wherein the stress inducing layer extends to the first and second junction regions. 
     
     
       7. A semiconductor device comprising;
 a substrate; 
 a fin shaped semiconductor region on the substrate, the fin shaped semiconductor region including a channel region and first and second junction regions on opposite sides of the channel region; 
 a gate electrode disposed over the fin shaped semiconductor region; and 
 a stress inducing layer comprising a continuous layer of a same material, 
 wherein a surface of the channel region of the fin shaped semiconductor region has a portion defining a carrier passage between the first and second junction regions and a portion being stressed by the stress inducing layer, wherein the stress inducing layer is provided along a surface of the fin shaped semiconductor region opposite the substrate so that portions of the fin shaped semiconductor region are between the stress inducing layer and the substrate, and wherein the stress inducing layer is provided along portions of a sidewall of the fin shaped semiconductor region extending continuously between the first and second junction regions. 
 
     
     
       8. A semiconductor device according to  claim 7 , wherein the gate electrode extends across a surface of the fin shaped semiconductor region opposite the substrate and along a portion of the sidewall of the fin shaped semiconductor region. 
     
     
       9. A semiconductor device according to  claim 7  wherein portions of the stress inducing layer are between the gate electrode and the substrate. 
     
     
       10. A semiconductor device comprising;
 a substrate; 
 an active semiconductor region on the substrate, the active semiconductor region having a channel region between first and second junction regions; 
 a gate electrode on the channel region; and 
 a stress inducing layer, wherein the stress inducing layer comprises at least one of silicon oxide and silicon nitride; 
 wherein the channel region comprises a first semiconductor material, the first and second junction regions comprise a second semiconductor material and the first and second semiconductor materials are different. 
 
     
     
       11. A semiconductor device according to  claim 10 , wherein the first and second semiconductor materials have different lattice constants. 
     
     
       12. A semiconductor device comprising;
 a substrate; 
 an active semiconductor region on the substrate, the active semiconductor region having a channel region between first and second junction regions wherein the active semiconductor region comprises a fin shaped active semiconductor region; 
 a gate electrode on the channel region; and 
 a stress inducing layer wherein the stress inducing layer is between the gate electrode and the substrate; 
 wherein the channel region comprises a first semiconductor material, the first and second junction regions comprise a second semiconductor material and the first and second semiconductor materials are different. 
 
     
     
       13. A semiconductor device according to  claim 12 , wherein the stress inducing layer comprises at least one of silicon oxide and silicon nitride. 
     
     
       14. A semiconductor device according to  claim 12 , wherein the stress inducing layer is formed along a surface of the fin shaped semiconductor region opposite the substrate. 
     
     
       15. A semiconductor device according to  claim 12 , wherein the stress inducing layer is formed along a sidewall of the fin shaped semiconductor region. 
     
     
       16. A semiconductor device according to  claim 12 , wherein the stress inducing layer extends to the first and second junction regions. 
     
     
       17. A semiconductor device according to  claim 12 , wherein the first and second semiconductor materials have different lattice constants. 
     
     
       18. A semiconductor device according to  claim 12 , wherein the stress inducing layer is formed along a surface of the fin shaped semiconductor region opposite the substrate so that portions of the fin shaped semiconductor region are between the stress inducing layer and the substrate. 
     
     
       19. A semiconductor device according to  claim 12 , wherein the stress inducing layer extends continuously between the first and second junction regions across the channel region.