Memory device and memory system comprising same

Abstract

A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.

What is claimed is: 
     
       1. A memory device comprising:
 a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells; 
 a control setting circuit configured to group the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and further configured to respectively set first control parameters for the first group and second control parameters, different from the first control parameters, for the second group, 
 wherein the presence or absence of at least one substandard memory cell in each memory block is determined based on test results obtained by performing a test on each memory block with respect to at least one control parameter, 
 each memory block in the first group comprises at least one substandard memory cell, 
 each memory block in the second group comprises no substandard memory cell, and 
 memory cells of the first group are respectively accessed according to the first control parameters and memory cells of the second group are respectively accessed according to the second control parameters during operation of the memory device. 
 
     
     
       2. The memory device of  claim 1 , wherein the memory blocks are grouped into the first and second groups by selecting an address code for the memory blocks. 
     
     
       3. The memory device of  claim 1 , wherein the control setting circuit selectively enables memory blocks of the first and second groups. 
     
     
       4. The memory device of  claim 1 , wherein each of the first control parameters and the second control parameters includes at least one alternating current (AC) parameter of the memory cells, and
 the control setting circuit comprises: 
 a status register that stores the test result and provides status information regarding the test result; and 
 an address mapper unit configured to convert logical addresses of the memory blocks into physical addresses of the first and second groups based on the status information. 
 
     
     
       5. The memory device of  claim 4 , wherein the control setting circuit further comprises:
 a pulse generator configured to generate an enable pulse signal to selectively enable the memory blocks of the first and second groups in response to a flag signal indicating a data storage capacity required by the memory device. 
 
     
     
       6. The memory device of  claim 4 , wherein the address mapper unit converts the logical addresses of the memory blocks into the physical addresses of the first and second groups using disable signals corresponding to the logical addresses. 
     
     
       7. The memory device of  claim 6 , wherein the disable signals are provided from a mode register set. 
     
     
       8. The memory device of  claim 4 , wherein the address mapper unit converts the logical addresses of the memory blocks into the physical addresses of the first and second groups using phase inversion signals corresponding to the logical addresses. 
     
     
       9. The memory device of  claim 8 , wherein the phase inversion signals are provided from a mode register set. 
     
     
       10. The memory device of  claim 4 , wherein the address mapper unit converts row logical addresses and column logical addresses of the memory blocks into row physical addresses and column physical addresses of the first and second groups. 
     
     
       11. The memory device of  claim 10 , wherein the address mapper unit provides the row logical addresses to a row address decoder to enable wordlines connected to the memory cells and provides the column logical addresses to a column address decoder to enable bitlines connected to the memory cells. 
     
     
       12. The memory device of  claim 10 , wherein the address mapper unit comprises:
 a first address mapper configured to convert the row logical addresses into the row physical addresses to be provided to a row address decoder to enable wordlines connected to the memory cells; and 
 a second address mapper configured to convert the column logical addresses into the column physical addresses to be provided to a column address decoder to enable bitlines connected to the memory cells. 
 
     
     
       13. The memory device of  claim 1 , wherein the memory device operates as a partial chip based on a distribution of the substandard memory cells within the memory blocks. 
     
     
       14. The memory device of  claim 13 , wherein the memory device operates as a half chip based on a distribution of the substandard memory cells within the memory blocks. 
     
     
       15. The memory device of  claim 13 , wherein the memory device operates as a quad chip based on a distribution of the substandard memory cells within the memory blocks. 
     
     
       16. A memory system, comprising:
 a memory device comprising: 
 a plurality of memory blocks each comprising a plurality of memory cells; and 
 a control setting circuit configured to group the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and further configured to respectively set first control parameters for the first group and second control parameters, different from the first control parameters, for the second group, wherein the presence or absence of at least one substandard memory cell in each memory block is determined based on test results obtained by performing a test on each memory block with respect to at least one control parameter, each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell; and 
 a memory controller configured to control operations of the memory device, wherein memory cells of the first group are respectively accessed by the memory controller according to the first control parameters, and memory cells of the second group are respectively accessed by the memory controller according to the second control parameters. 
 
     
     
       17. The memory system of  claim 16 , wherein the memory device is a dynamic random access memory device. 
     
     
       18. An application system comprising:
 a bus; 
 a microprocessor connected to the bus; and 
 a memory device configured to store data to be processed by the microprocessor, the memory device comprising: 
 a memory cell array comprising a plurality of memory blocks, each having a plurality of memory cells; and 
 a control setting circuit configured to divide the memory blocks into at least first and second groups based on whether the each of the memory blocks comprises at least one substandard memory cell, and further configured to respectively set first control parameters including at least one alternating current (AC) parameter for the first group and second control parameters, different from the first control parameters and including at least one AC parameter for the second group, wherein the substandard memory cells are identified based on test results obtained through a test performed on the memory cells with respect to at least one control parameter, the first group comprises at least one substandard memory cell, the second group comprises no substandard memory cell, and memory cells of the first group are respectively accessed according to the first control parameters and memory cells of the second group are respectively accessed according to the second control parameters during operation of the memory device. 
 
     
     
       19. The application system of  claim 18 , wherein the at least one AC parameter comprises at least one of; a row address signal (RAS) to column address signal (CAS) delay time, a RAS precharge time, and a CAS precharge time. 
     
     
       20. The application system of  claim 18 , wherein the memory device comprises a dynamic random access memory.