Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof

Abstract

A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, the method comprising:
 providing a workpiece; 
 forming active areas over or within the workpiece; 
 forming a plurality of input/output cells over at least one active area; and 
 coupling a first bond pad and at least one second bond pad to each input/output cell; 
 wherein coupling the first bond pad comprises forming the first bond pad in a first pattern, wherein coupling the at least one second bond pad comprises forming the second bond pad in at least one second pattern, the at least one second pattern being different from the first pattern, wherein forming each first bond pad comprises disposing a center of the first bond pad over an input/output cell to which the first bond pad is coupled, and wherein forming each at least one second bond pad comprises disposing the at least one second bond pad near a side of and spaced apart from a respective one of the plurality of input/output cells. 
 
     
     
       2. The method according to  claim 1 , wherein coupling the first bond pad and the at least one second bond pad comprise simultaneously forming each first bond pad and each at least one second bond pad. 
     
     
       3. The method according to  claim 1 , wherein the first pattern comprises a straight in-line pattern, and wherein one of the at least one second patterns comprises a staggered pattern. 
     
     
       4. The method according to  claim 1 , wherein the first pattern and the at least one second pattern comprise a traditional bond pad pattern, a contact-under-pad (CUP) pattern, a ground-up flip chip bump pattern, a staggered pattern, an in-line pattern, or an area array bump pattern. 
     
     
       5. The method according to  claim 1 , further comprising forming at least one conductive pin disposed between and electrically coupling each first bond pad and each at least one second bond pad to the input/output cell. 
     
     
       6. The method according to  claim 1 , wherein forming the plurality of input/output cells comprises forming at least one of the input/output cells including level shifters, output buffers, input sensing circuits, or other circuitry. 
     
     
       7. A method of fabricating an integrated circuit die comprising:
 forming a plurality of input/output cells in a substrate; 
 forming a plurality of first bond pads disposed over the input/output cells in a first pattern, wherein each first bond pad is electrically coupled to one of the underlying input/output cells over which each respective first bond pad is primarily disposed; and 
 forming a plurality of second bond pads disposed proximate the input/output cells in a second pattern, each second bond pad being spaced apart from and disposed near a side of an input/output cell, each second bond pad being electrically coupled to a first input/output cell of the plurality of input/output cells, wherein the second pattern is different from the first pattern. 
 
     
     
       8. The method according to  claim 7 , wherein each first bond pad and each second bond pad are adapted to couple the integrated circuit die to a connection external to the integrated circuit die. 
     
     
       9. The method according to  claim 7 , wherein the first pattern comprises a straight in-line pattern, and wherein the second pattern comprises a staggered pattern. 
     
     
       10. The method according to  claim 7 , further comprising at least one conductive pin disposed between and electrically coupling each first bond pad and each second bond pad to the first input/output cell. 
     
     
       11. The method according to  claim 10 , wherein the first bond pads and the second bond pads are formed in a bond pad layer disposed over the input/output cells, wherein the at least one conductive pin comprises a conductive line formed in the bond pad layer. 
     
     
       12. The method according to  claim 7 , further comprising packaging the integrated circuit die. 
     
     
       13. The method according to  claim 12 , wherein the packaged integrated circuit die includes a plurality of leads, each lead being coupled to a first bond pad or a second bond pad of the integrated circuit die. 
     
     
       14. The method according to  claim 7 , further comprising forming a plurality of third bond pads disposed proximate the input/output cells, wherein each third bond pad is electrically coupled to one of the underlying input/output cells. 
     
     
       15. The method according to  claim 7 , wherein the first bond pads or the second bond pads are adapted to bond to a semiconductor device using wire, flip chip, tape automated, direct copper ball-ball, ball-wedge, or wedge-wedge bonding techniques.