Inventor
CHEN KER-MIN
TW34 patents
⚠️ This page may combine multiple inventors who share the name “CHEN KER-MIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
29 patentsUS7330702B2Feb 12, 2008
Method and apparatus for inter-chip wireless communication
TAIWAN SEMICONDUCTOR MFG89 citations97
US7221551B2May 22, 2007
Cascaded gate-driven ESD clamp
TAIWAN SEMICONDUCTOR MFG51 citations92
US7173472B2Feb 6, 2007
Input buffer structure with single gate oxide
TAIWAN SEMICONDUCTOR MFG27 citations92
US7151391B2Dec 19, 2006
Integrated circuit for level-shifting voltage levels
TAIWAN SEMICONDUCTOR MFG20 citations92
US7151400B2Dec 19, 2006
Boost-biased level shifter
TAIWAN SEMICONDUCTOR MFG51 citations92
US7071561B2Jul 4, 2006
Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell
TAIWAN SEMICONDUCTOR MFG17 citations92
US6306745B1Oct 23, 2001
Chip-area-efficient pattern and method of hierarchal power routing
TAIWAN SEMICONDUCTOR MFG32 citations92
US7594198B2Sep 22, 2009
Ultra fine pitch I/O design for microchips
TAIWAN SEMICONDUCTOR MFG17 citations84
US7557413B2Jul 7, 2009
Serpentine ballasting resistors for multi-finger ESD protection device
TAIWAN SEMICONDUCTOR MFG8 citations84
US7417837B2Aug 26, 2008
ESD protection system for multi-power domain circuitry
TAIWAN SEMICONDUCTOR MFG9 citations84
US7362136B2Apr 22, 2008
Dual voltage single gate oxide I/O circuit with high voltage stress tolerance
TAIWAN SEMICONDUCTOR MFG13 citations84
US7221183B2May 22, 2007
Tie-high and tie-low circuit
TAIWAN SEMICONDUCTOR MFG12 citations84
US7193441B2Mar 20, 2007
Single gate oxide I/O buffer with improved under-drive feature
TAIWAN SEMICONDUCTOR MFG18 citations84
US7884643B2Feb 8, 2011
Low leakage voltage level shifting circuit
TAIWAN SEMICONDUCTOR MFG7 citations83
US7795939B2Sep 14, 2010
Method and system for setup/hold characterization in sequential cells
TAIWAN SEMICONDUCTOR MFG12 citations83
US7248076B2Jul 24, 2007
Dual-voltage three-state buffer circuit with simplified tri-state level shifter
TAIWAN SEMICONDUCTOR MFG7 citations74
US6563353B2May 13, 2003
Circuit to eliminate bus contention at chip power up
TAIWAN SEMICONDUCTOR MFG9 citations74
US6479845B2Nov 12, 2002
Pattern for routing power and ground for an integrated circuit chip
TAIWAN SEMICONDUCTOR MFG8 citations74
US7865852B2Jan 4, 2011
Method for automatically routing multi-voltage multi-pitch metal lines
TAIWAN SEMICONDUCTOR MFG5 citations63
US7649214B2Jan 19, 2010
ESD protection system for multiple-domain integrated circuits
TAIWAN SEMICONDUCTOR MFG3 citations63
US7420789B2Sep 2, 2008
ESD protection system for multi-power domain circuitry
TAIWAN SEMICONDUCTOR MFG6 citations63
US7295052B2Nov 13, 2007
Regenerative power-on control circuit
TAIWAN SEMICONDUCTOR MFG4 citations63
US7168021B2Jan 23, 2007
Built-in test circuit for an integrated circuit device
TAIWAN SEMICONDUCTOR MFG5 citations63
US7142017B2Nov 28, 2006
High-voltage-tolerant feedback coupled I/O buffer
TAIWAN SEMICONDUCTOR MFG5 citations63
US7062740B2Jun 13, 2006
System and method for reducing design cycle time for designing input/output cells
TAIWAN SEMICONDUCTOR MFG3 citations62
US7714362B2May 11, 2010
Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof
TAIWAN SEMICONDUCTOR MFG0 citations52
US7500214B2Mar 3, 2009
System and method for reducing design cycle time for designing input/output cells
TAIWAN SEMICONDUCTOR MFG0 citations51
US7941770B2May 10, 2011
System and method for implementing an online design platform for integrated circuits
TAIWAN SEMICONDUCTOR MFG0 citations42
US7274544B2Sep 25, 2007
Gate-coupled ESD protection circuit for high voltage tolerant I/O
TAIWAN SEMICONDUCTOR MFG0 citations42
CHEN KER-MIN
3 patentsUS8501622B2Aug 6, 2013
Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof
CHEN KER-MIN0 citations49
US8492795B1Jul 23, 2013
Integrated circuit having input/output cell array having single gate orientation
CHEN KER-MIN1 citations49
US8943453B2Jan 27, 2015
Automatic application-rule checker
CHEN KER-MIN0 citations39