Semiconductor device and method of manufacturing same

Abstract

There is provided a semiconductor device and a manufacturing method therefor, the semiconductor device requiring flip-chip mounting of a fine pitch electrode, wherein the fine electrode is easily manufactured, resin sealing is not required, and reliability can be improved. In the semiconductor device, one or more LSI chips ( 1 ), having an insulating layer ( 3 ) surface and an electrode ( 2 ) surface on one side, and a substrate ( 4 ), having an insulating layer ( 6 ) surface and an electrode ( 5 ) surface on one side, are bonded by having surfaces of the electrodes and surfaces of the insulating layers face each other via a bonding layer ( 7 ) made in a thin film form, in a region excluding the surfaces of the electrodes ( 2, 5 ) and the surfaces of the insulating layers ( 3, 6 ) in areas surrounding the electrodes.

What is claimed is: 
     
       1. A semiconductor device wherein at least one LSI chip having an insulating layer surface and an electrode surface on one side and a substrate having an insulating layer surface and an electrode surface on one side are bonded by having said electrode surfaces and said insulating layer surfaces face each other, via a bonding layer made in a thin film form in a region excepting said electrode surfaces and said insulating layer surfaces in areas surrounding said electrodes,
 wherein said bonding layer is a metal bonding layer including at least one of any of the elements: Cu, Ni, Pd, Sn, Au, and In, or a combination of a plurality thereof. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein said bonding layer in said thin film form is formed also on a bonding surface of said electrode surfaces. 
     
     
       3. The semiconductor device according to  claim 1 , wherein said bonding layer is a thin film form bonding layer formed on a single flat surface. 
     
     
       4. The semiconductor device according to  claim 1 , wherein said bonding layer has a thickness of greater than or equal to 0.05 μm and less than or equal to 3 μm. 
     
     
       5. The semiconductor device according to  claim 1 , wherein voids are formed in a portion of the insulating layer surface in an area surrounding said electrode of said LSI chip and in a portion of the insulating layer surface in an area surrounding said electrode of said substrate. 
     
     
       6. The semiconductor device according to  claim 1 , wherein a resin is filled into the portion of the insulating layer surface in the area surrounding of said electrode of said LSI chip and into the portion of the insulating layer surface in the area surrounding said electrode of said substrate. 
     
     
       7. The semiconductor device according to  claim 1 , wherein said insulating layer surface of said LSI chip or said substrate is formed of an organic film. 
     
     
       8. The semiconductor device according to  claim 7 , wherein the insulating layer of said LSI chip or said substrate is formed of one or more among polyimide, modified polyimide, and epoxy. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the insulating layer of said LSI chip or said substrate is formed of an inorganic film. 
     
     
       10. The semiconductor device according to  claim 9 , wherein the insulating layer of said LSI chip or said substrate is formed of one or more among silicon oxide film and silicon nitride film. 
     
     
       11. The semiconductor device according to  claim 1 , wherein said bonding layer is a structure partially having openings. 
     
     
       12. A method of manufacturing a semiconductor device comprising:
 flattening an electrode and an insulating layer of each of an LSI chip and a substrate, 
 disposing a catalyst in order to form an electroless plating on surfaces of said flattened electrode and insulating layer, 
 removing only said catalyst disposed on said electrode and said insulating layer surface in an area surrounding said electrode, 
 forming a bonding layer of a thin film form on said insulating layer surfaces and said electrodes by processing of said electroless plating, 
 arranging positions of said electrodes of each of said LSI chip and said substrate, and 
 heating and pressurizing, 
 wherein said bonding layer is a metal bonding layer including at least one of any of the elements: Cu, Ni, Pd, Sn, Au, and In, or a combination of a plurality thereof. 
 
     
     
       13. A method of manufacturing a semiconductor device comprising:
 flattening an electrode and an insulating layer of each of an LSI chip and a substrate; 
 disposing a catalyst in order to form an electroless plating on surfaces of said flattened electrode and insulating layer; 
 removing only said catalyst disposed on said electrode and said insulating layer surface in an area surrounding said electrode; 
 forming a bonding layer of a thin film form on said insulating layer surfaces by processing of said electroless plating, 
 arranging positions of said electrodes of each of said LSI chip and said substrate; and 
 heating and pressurizing, 
 wherein said bonding layer is a metal bonding layer including at least one of any of the elements: Cu, Ni, Pd, Sn, Au, and In, or a combination of a plurality thereof. 
 
     
     
       14. The method of manufacturing said semiconductor device according to  claim 12 , further comprising:
 performing surface reformation on an upper surface of said flattened electrode and insulating layer, before said disposing said catalyst in order to form said electroless plating. 
 
     
     
       15. The method of manufacturing said semiconductor device according to  claim 13 , further comprising:
 performing surface reformation on an upper surface of said flattened electrode and insulating layer, before said disposing said catalyst in order to form said electroless plating.