US8535984B2ActiveUtilityPatentIndex 81
Electronic modules and methods for forming the same
Est. expiryApr 4, 2028(~1.8 yrs left)· nominal 20-yr term from priority
H10W 70/682H10W 74/142H10W 90/722H10W 70/681H10W 70/60H10W 72/9413H10W 46/301H10W 46/601H10W 70/093H10W 90/00H10P 72/7438H10P 72/743H10P 72/74H10W 74/131H10W 74/15H10W 74/012H10W 74/10H10W 70/635H10W 70/614H10W 70/611H10W 46/00H10W 74/01
81
PatentIndex Score
13
Cited by
215
References
12
Claims
Abstract
Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A method for electrically connecting a plurality of microelectronic dies, the method comprising:
disposing the plurality of microelectronic dies on a single adhesive layer in a plurality of positions, each die thereafter having at least one exposed surface, the plurality of positions determined at least in part by a die placement mask located near the microelectronic dies;
placing the adhesive layer in contact with a substrate having a first side and a second side, the second side comprising a plurality of cavities, the cavities located at a plurality of positions corresponding to the positions of the microelectronic dies so as to receive the microelectronic dies;
applying an encapsulant over the exposed surfaces of the microelectronic dies so as to encapsulate each microelectronic die;
removing at least a portion of the adhesive layer from each microelectronic die; and thereafter forming at least one electrical connection between at least two of the microelectronic dies.
2. The method of claim 1 further comprising curing the applied encapsulant over a period of time.
3. The method of claim 1 further comprising:
forming a plurality of fill holes in the first side of the substrate, each cavity being in fluidic communication with at least one fill hole; and
applying the encapsulant by injecting it through the fill holes.
4. The method of claim 3 further comprising forming at least one post within at least one of the cavities.
5. The method of claim 4 , wherein the post is formed during formation of the cavity.
6. The method of claim 5 , wherein both the post and the cavity are formed by etching the substrate.
7. The method of claim 4 , wherein the post and the substrate each comprise the same material.
8. The method of claim 4 , wherein the post and the substrate each comprise a semiconductor material.
9. The method of claim 8 , wherein the post and the substrate each comprise silicon.
10. The method of claim 4 further comprising forming a conductive material over the post and an interior surface of the cavity.
11. The method of claim 10 , wherein at least a portion of the electrical connection comprises the post.
12. The method of claim 1 , wherein the adhesive layer comprises a dielectric material.Cited by (0)
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