Method of forming polysilicon resistor during replacement metal gate process and semiconductor device having same

Abstract

A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a surface of a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion in a recessed portion of the substrate below the surface of the substrate, the resistor portion including a third polysilicon layer, and removing the first and second polysilicon layers from the first and second gate stack portions to expose the first and second gate oxide layers, wherein at least one of a dielectric layer and a stress liner cover a top surface of the resistor portion during removal of the first and second polysilicon layers.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor device, comprising:
 forming a first gate stack portion on a surface of a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer; 
 forming a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer; 
 forming a resistor portion in a recessed portion of the substrate below the surface of the substrate, the resistor portion including a third polysilicon layer; and 
 removing the first and second polysilicon layers from the first and second gate stack portions to expose the first and second gate oxide layers, wherein at least one of a dielectric layer and a stress liner cover a top surface of the resistor portion during removal of the first and second polysilicon layers. 
 
     
     
       2. The method for manufacturing the semiconductor device according to  claim 1 , wherein removing the first and second polysilicon layers comprises etching using at least one of ammonia, tetramethyl ammonium hydroxide (TMAH), and tetraethylammonium hydroxide (TEAH). 
     
     
       3. The method for manufacturing the semiconductor device according to  claim 1 , wherein the recessed portion is formed by etching a portion of an isolation region formed below the surface of the substrate. 
     
     
       4. The method for manufacturing the semiconductor device according to  claim 1 , further comprising:
 depositing a high-K dielectric material on exposed portions of the substrate, including the first and second gate oxide layers; and 
 depositing a first metal on the high-K dielectric layer. 
 
     
     
       5. The method for manufacturing the semiconductor device according to  claim 1 , wherein removing the first and second polysilicon layers is performed in a single step. 
     
     
       6. A computer system comprising a semiconductor device having a circuit layout manufactured by the method of  claim 1 , wherein the computer system is one of a personal computer (PC), a personal digital assistant (PDA), an MP3 player, a digital audio recorder, a pen-shaped computer, a digital camera, or a video recorder. 
     
     
       7. A semiconductor memory card, comprising:
 an interface part that interfaces with an external device; 
 a controller that communicates with the interface part and a memory device via address and data buses, wherein the memory device comprises a circuit layout manufactured by the method of  claim 1 . 
 
     
     
       8. The method for manufacturing the semiconductor device according to  claim 3 , wherein the recessed portion has a depth of about 100 angstroms to 400 angstroms below the surface of the substrate. 
     
     
       9. The method for manufacturing the semiconductor device according to  claim 3 , further comprising:
 depositing, prior to removing the first and second polysilicon layers from the first and second gate stack portions, the at least one of the dielectric layer and the stress liner on the substrate adjacent and between the first and second gate stack portions and the resistor portion, and over the resistor portion; and 
 performing a chemical mechanical polishing to remove part of the at least one of the dielectric layer and the stress liner to planarize a top surface of the semiconductor device to be level with a top of the first and second gate stack portions, leaving the at least one of a dielectric layer and a stress liner covering the top surface of the resistor portion. 
 
     
     
       10. The method for manufacturing the semiconductor device according to  claim 9 , further comprising:
 depositing a high-K dielectric material on exposed portions of the substrate, including the first and second gate oxide layers; and 
 depositing a metal on the high-K dielectric layer. 
 
     
     
       11. The method for manufacturing the semiconductor device according to  claim 10 , further comprising:
 performing a chemical mechanical polishing to remove the high-K dielectric material, and the metal from a top surface of the semiconductor device, and to planarize the top surface of the semiconductor device; and 
 removing the at least one of the dielectric layer and the stress liner from the substrate except for a portion of the at least one of the dielectric layer and the stress liner in the recessed portion. 
 
     
     
       12. The method for manufacturing the semiconductor device according to  claim 4 , wherein the first metal comprises a three-layer structure of a bottom layer of TiN, a middle layer of TaN and a top layer of TiN. 
     
     
       13. The method of manufacturing the semiconductor device according to  claim 12 , further comprising:
 forming a photoresist covering the second gate stack portion and the resistor portion; and 
 removing the top layer of TiN from the first gate stack portion. 
 
     
     
       14. The method for manufacturing the semiconductor device according to  claim 13 , further comprising:
 removing the photoresist; and 
 depositing a second metal on exposed portions of the substrate, including the first and second gate stack portions. 
 
     
     
       15. The method for manufacturing the semiconductor device according to  claim 14 , wherein the second metal comprises a three-layer structure of a bottom layer of TiAl, a middle layer of TiN, and a top layer of titanium and aluminum alloy (Ti/Al). 
     
     
       16. The method for manufacturing the semiconductor device according to  claim 14 , further comprising:
 performing a chemical mechanical polishing to remove the high-K dielectric material, the first metal and the second metal from a top surface of the semiconductor device, and to planarize the top surface of the semiconductor device. 
 
     
     
       17. A method for manufacturing a semiconductor device, comprising:
 forming a plurality of isolation regions in a substrate; 
 depositing a gate oxide layer on a surface of the substrate including the plurality of isolation regions; 
 depositing a first polysilicon layer on the gate oxide layer; 
 forming a photoresist on part of the polysilicon layer, wherein a portion of the polysilicon layer over an isolation region remains exposed; 
 removing the exposed portion of the polysilicon layer, and portions of the gate oxide layer and the isolation region under the exposed portion of the polysilicon layer to form a recessed portion below the surface of the substrate; 
 removing the photoresist; 
 depositing a second polysilicon layer in the recessed portion and on the substrate including the first polysilicon layer; and 
 doping a portion of the second polysilicon layer formed in the recessed portion. 
 
     
     
       18. The method for manufacturing the semiconductor device according to  claim 17 , wherein the portion of the second polysilicon layer in the recessed portion is doped with boron. 
     
     
       19. The method for manufacturing the semiconductor device according to  claim 17 , wherein the recessed portion has a depth of about 100 angstroms to 400 angstroms below the surface of the substrate. 
     
     
       20. The method for manufacturing the semiconductor device according to  claim 17 , wherein the portion of the second polysilicon layer formed in the recessed portion forms a resistor of the semiconductor device. 
     
     
       21. A system for transmitting or receiving data, the system comprising:
 a memory device for storing a program; and 
 a processor in communication with the memory device, wherein the memory device comprises: 
 a substrate; 
 a first gate stack portion on a surface of the substrate, the first gate stack portion including a first gate oxide layer and a first metal layer on the first gate oxide layer; 
 a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second metal layer on the second gate oxide layer; and 
 a resistor portion positioned in a recessed portion below the surface of the substrate, the resistor portion including a polysilicon layer, wherein a top surface of the resistor portion is positioned below top surfaces of the first and second gate stack portions. 
 
     
     
       22. The system according to  claim 21 , wherein the system comprises at least one of a mobile system, a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card. 
     
     
       23. A semiconductor memory card, comprising:
 an interface part that interfaces with an external device; 
 a controller that communicates with the interface part and a memory device via address and data buses, wherein the memory device comprises: 
 a substrate; 
 a first gate stack portion on a surface of the substrate, the first gate stack portion including a first gate oxide layer and a first metal layer on the first gate oxide layer; 
 a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second metal layer on the second gate oxide layer; and a resistor portion positioned in a recessed portion below the surface of the substrate, the resistor portion including a polysilicon layer, wherein a top surface of the resistor portion is positioned below top surfaces of the first and second gate stack portions. 
 
     
     
       24. A system for transmitting or receiving data, the system comprising:
 a memory device for storing a program; and 
 a processor in communication with the memory device, wherein the memory device comprises a circuit layout manufactured by the method of  claim 1 . 
 
     
     
       25. The system according to  claim 24 , wherein the system comprises at least one of a mobile system, a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.