Patterning method for fabrication of a semiconductor device

Abstract

A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.

What is claimed is: 
     
       1. A method of fabricating a semiconductor device, the method comprising:
 forming an organic planarization layer overlying a semiconductor device structure having conductive contact elements; 
 forming an antireflective coating layer overlying the organic planarization layer; 
 forming a photoresist layer overlying the antireflective coating layer; 
 removing portions of the photoresist layer to create a patterned photoresist layer having openings corresponding to the conductive contact elements; 
 plasma etching the antireflective coating layer using the patterned photoresist layer as a first etch mask, resulting in a patterned antireflective coating layer, wherein the plasma etching forms openings with inwardly tapered sidewalls in the antireflective coating layer, and wherein the openings terminate at exposed portions of an upper surface of the organic planarization layer; 
 after the plasma etching, directionally etching the organic planarization layer using the patterned antireflective coating layer as a second etch mask, resulting in a patterned organic planarization layer having recesses formed therein, wherein the directional etching forms the recesses with vertical sidewalls defined by, and aligned with, bottom perimeter shapes of the openings in the patterned antireflective coating layer; 
 after the directional etching, depositing a conformal liner within the recesses; and 
 etching the conformal liner to expose an interlayer dielectric of the semiconductor device structure. 
 
     
     
       2. The method of  claim 1 , wherein directionally etching the organic planarization layer exposes portions of the interlayer dielectric. 
     
     
       3. The method of  claim 2 , wherein forming the conformal liner comprises conformally depositing a liner material overlying exposed portions of the interlayer dielectric and on exposed sidewalls of the patterned organic planarization layer. 
     
     
       4. The method of  claim 1 , wherein:
 etching the conformal liner results in lined sidewalls for the recesses formed in the organic planarization layer; and 
 the method further comprises etching the interlayer dielectric to form contact recesses in the interlayer dielectric, the contact recesses having sidewalls aligned with and defined by the lined sidewalls. 
 
     
     
       5. The method of  claim 4 , further comprising:
 removing residual portions of the patterned antireflective coating layer; 
 removing residual portions of the patterned organic planarization layer; and 
 removing residual portions of the conformal liner. 
 
     
     
       6. The method of  claim 5 , further comprising creating conductive plugs in the contact recesses, the conductive plugs corresponding to the conductive contact elements of the semiconductor device structure. 
     
     
       7. A method of fabricating a semiconductor device, the method comprising:
 forming an organic planarization layer overlying a semiconductor device structure having conductive contact elements; 
 forming an antireflective coating layer overlying the organic planarization layer; 
 forming a photoresist layer overlying the antireflective coating layer; 
 removing portions of the photoresist layer to create a patterned photoresist layer having openings corresponding to the conductive contact elements; 
 plasma etching the antireflective coating layer using the patterned photoresist layer as a first etch mask, resulting in a patterned antireflective coating layer having openings defined therein, wherein the openings are formed with inwardly tapered sidewalls, and wherein the openings terminate at exposed portions of an upper surface of the organic planarization layer; 
 after the plasma etching, forming a conformal liner overlying the patterned antireflective coating layer and within the openings defined in the patterned antireflective coating layer; 
 directionally etching the conformal liner to expose portions of an upper surface of the organic planarization layer, wherein directionally etching the conformal liner results in lined sidewalls for the openings defined in the patterned antireflective coating layer; and 
 after etching the conformal liner, directionally etching the organic planarization layer using the patterned antireflective coating layer and the lined sidewalls as a second etch mask, resulting in a patterned organic planarization layer, wherein directionally etching the organic planarization layer forms recesses with vertical sidewalls defined by lowermost dimensions of the lined sidewalls, and aligned with, bottom. 
 
     
     
       8. The method of  claim 7 , wherein:
 directionally etching the organic planarization layer exposes portions of an interlayer dielectric of the semiconductor device structure; and 
 the method further comprises etching the interlayer dielectric, using the patterned organic planarization layer as a third etch mask, to form contact recesses in the interlayer dielectric. 
 
     
     
       9. The method of  claim 8 , further comprising creating conductive plugs in the contact recesses, the conductive plugs corresponding to the conductive contact elements of the semiconductor device structure. 
     
     
       10. The method of  claim 7 , wherein forming the conformal liner comprises conformally depositing a liner material overlying exposed portions of the organic planarization layer.