Non-volatile FINFET memory array and manufacturing method thereof

Abstract

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

We claim: 
     
       1. An electronic device, comprising:
 a substrate comprising a semiconducting layer, said semiconducting layer further comprising a plurality of fin-type projections laterally coextending in a first direction through a memory cell region of said substrate and select gate regions of said substrate abutting said memory cell region; 
 a dielectric isolation material disposed 1n spaces between said plurality of fin-type projections, said dielectric isolation material in said memory cell regions having a height less than a height of plurality of fin-type projections in said memory cell regions, and said dielectric isolation material in said abutting select gate regions having a height greater than or equal to than a height of said plurality of fin-type projections in said abutting select gate regions; 
 a plurality of gate features disposed on said substrate within said memory cell region and said abutting select gate regions over said plurality of projections and said dielectric isolation material, said plurality of gate features coextending in a second direction transverse to said first direction. 
 
     
     
       2. The device of  claim 1 , wherein said portion of said plurality of gate features in said memory cell and said plurality of gate features in said abutting select gate regions are configured to have at least one of a different width and a different pitch. 
     
     
       3. The device of  claim 1 , Wherein said portion of said plurality of gate features in said memory cell have a first pitch and said plurality of gate features in said abutting select gate regions to have second pitch greater than said first pitch. 
     
     
       4. The device of  claim 1 , wherein said portion of said plurality of gate features in said memory cell have a first linewidth and said plurality of gate features in said abutting select gate regions to have second linewidth greater than said first linewidth. 
     
     
       5. The device of  claim 1 , further comprising:
 a control element communicatively coupled to said plurality of gate features to provide a memory system; and 
 an electronic system coupled to said memory system. 
 
     
     
       6. An integrated circuit, comprising:
 a substrate comprising a semiconducting surface; and 
 a NAND-type memory array formed on or in said semiconducting surface, said memory array comprising a plurality of memory cell devices formed in memory cell regions of said memory array and a plurality of select gate devices formed in select gate regions of said memory array abutting said memory cell regions, wherein said plurality of memory cell devices comprising fin-type transistor devices and said plurality of select gate devices comprising planar transistor devices. 
 
     
     
       7. In the integrated circuit of  claim 6 , wherein said memory array further comprises:
 a first plurality of fin-type projections laterally coextending in a first direction through a memory cell region of said substrate and select gate regions of said substrate abutting said memory cell region; and 
 a dielectric isolation material disposed in spaces between said first and said second plurality of fin-type projections, said dielectric isolation material in said memory cell regions having a height less than a height of said fin-type projections in said memory ceil regions to define said plurality of memory cell devices, and said dielectric isolation material in said abutting select gate regions having a height greater than or equal to than a height of said fin-type projections in said abutting select gate regions to define said plurality of select gate devices. 
 
     
     
       8. The integrated circuit of  claim 6 , wherein a plurality of gate features for said plurality of memory cell devices and a plurality of gate features for said plurality of select gate devices are configured to have at least one of a different width and a different pitch. 
     
     
       9. The integrated circuit of  claim 6 , wherein a plurality of gate features for said plurality of memory cell devices have a first pitch and a plurality of gate features for said plurality of select gate devices have a second pitch greater than said first pitch. 
     
     
       10. The integrated circuit of  claim 6 , wherein a plurality of gate features for said plurality of memory cell devices have a first linewidth and a plurality of gate features for said plurality of select gate devices have a second linewidth greater than said first linewidth. 
     
     
       11. The device of  claim 6 , further comprising:
 a control element region formed on or in said semiconductor surface, and communicatively couple to said NAND-type memory array to form a memory system.