Inducement of strain in a semiconductor layer

Abstract

Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

What is claimed is: 
     
       1. A structure comprising:
 a first layer comprising a first semiconductor material disposed above a substrate, the first semiconductor material being strained; 
 a second layer disposed above the first layer, the second layer comprising a second semiconductor material different from the first semiconductor material; 
 a transistor gate electrode and a sidewall spacer disposed above the second layer, the transistor gate electrode and sidewall spacer defining a first region disposed thereunder, the first region comprising a first portion of each of the first layer and the second layer; and 
 a third material disposed laterally from the first region, the third material extending into the first layer and the second layer, 
 wherein at least one of a composition or defect density of the third material is different from a composition or defect density of the first region. 
 
     
     
       2. The structure of  claim 1 , wherein the third material is the same as the first semiconductor material. 
     
     
       3. The structure of  claim 1 , wherein third material is the same as the second semiconductor material. 
     
     
       4. The structure of  claim 1 , wherein the third material is different from the first semiconductor material and the second semiconductor material. 
     
     
       5. The structure of  claim 1 , wherein the third material comprises a second portion of each of the first layer and the second layer, the second portions having substantially higher crystalline defect densities than the first portions. 
     
     
       6. The structure of  claim 1 , further comprising a strain-inducing overlayer disposed above the first layer, the gate electrode, and the sidewall spacer. 
     
     
       7. A semiconductor structure comprising:
 a first semiconductor layer over a substrate, the first semiconductor layer having a relaxed portion and a strained portion; 
 a second semiconductor layer over the first semiconductor layer, the relaxed portion of the first semiconductor layer inducing strain in a portion of the second semiconductor layer; and 
 a third semiconductor material in a region laterally adjoining the first semiconductor layer and the second semiconductor layer. 
 
     
     
       8. The semiconductor structure of  claim 7 , wherein the third semiconductor material is disposed in a recess extending to a surface of the substrate. 
     
     
       9. The semiconductor structure of  claim 7 , wherein the third semiconductor material includes a combination of a first material of the first semiconductor layer and a second material of the second semiconductor layer. 
     
     
       10. The semiconductor structure of  claim 7 , wherein the substrate is a semiconductor-on-insulator (SOI) substrate or a strained semiconductor-on-insulator (SSOI) substrate. 
     
     
       11. The semiconductor structure of  claim 7  further comprising a gate electrode and a gate spacer on a sidewall of the gate electrode, a lateral edge of the gate spacer opposite from the gate electrode being laterally offset from an edge of the region nearest the gate spacer. 
     
     
       12. The semiconductor structure of  claim 7  further comprising a gate electrode and a gate spacer on a sidewall of the gate electrode, a lateral edge of the gate spacer opposite from the gate electrode adjoining an edge of the region. 
     
     
       13. The semiconductor structure of  claim 7  further comprising:
 a gate over the second semiconductor layer; and 
 a shallow trench isolation (STI) in the substrate and proximate the gate, the STI comprising an exterior liner and an interior insulating material, the interior insulating material having a top surface lower than a top surface of the substrate. 
 
     
     
       14. The semiconductor structure of  claim 7 , wherein the substrate comprises a graded buffer layer, the first semiconductor layer being disposed over the graded buffer layer. 
     
     
       15. A semiconductor structure comprising:
 a substrate having a first region and a second region; 
 a first semiconductor layer over the substrate in the first region and the second region; 
 a second semiconductor layer over the first semiconductor layer and in the first region and the second region; 
 a first transistor in the first region; and 
 a second transistor in the second region, 
 wherein at least a portion of the second semiconductor layer in the first region is strained, and at least a portion of the second semiconductor layer in the second region is relaxed. 
 
     
     
       16. The semiconductor structure of  claim 15 , wherein at least a portion of the first semiconductor layer in the first region is relaxed, and at least a portion of the first semiconductor layer in the second region is strained. 
     
     
       17. The semiconductor structure of  claim 15  further comprising a third semiconductor material in a source/drain region of the first transistor, the third semiconductor material being laterally disposed relative to the first semiconductor layer and the second semiconductor layer. 
     
     
       18. The semiconductor structure of  claim 17 , wherein the third semiconductor material is different in composition from a composition of the first semiconductor layer and a composition of the second semiconductor layer. 
     
     
       19. The semiconductor structure of  claim 17 , wherein the third semiconductor material is the same material as the substrate. 
     
     
       20. The semiconductor structure of  claim 15 , wherein the first transistor is an n-type transistor, and the second transistor is a p-type transistor.