Thin-film transistor array substrate, organic light emitting display device including the same, and method of manufacturing the same

Abstract

A TFT array substrate including: a thin-film transistor including an active layer, gate, source and drain electrodes, a first insulation layer between the active layer and the gate electrode, and a second insulation layer between the gate and the source and drain electrodes; a pixel electrode on the first and second insulation layers, and connected to one of the source and drain electrodes; a capacitor including a first electrode on the same layer as the gate electrode, a second electrode formed of the same material as the pixel electrode, a first protection layer on the second electrode, and a second protection layer on the first protection layer; a third insulation layer between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; and a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode.

What is claimed is: 
     
       1. An organic light emitting display device comprising:
 a thin-film transistor comprising:
 an active layer, 
 a gate electrode, 
 source and drain electrodes, 
 a first insulation layer disposed between the active layer and the gate electrode, and 
 a second insulation layer disposed between the gate electrode and the source and drain electrodes; 
 
 a pixel electrode disposed on the first and second insulation layers and connected to one of the source and drain electrodes; 
 a capacitor comprising:
 a first electrode disposed on the same layer as the gate electrode, 
 a second electrode formed of the same material as the pixel electrode, 
 a first protection layer disposed on the second electrode, and 
 a second protection layer disposed on the first protection layer; 
 
 a third insulation layer disposed between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; 
 a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode; 
 an organic light emitting layer disposed on the pixel electrode; and 
 a counter electrode disposed on the organic light emitting layer. 
 
     
     
       2. The organic light emitting display device of  claim 1 , wherein the counter electrode is a reflective electrode reflecting light emitted from the organic light emitting layer. 
     
     
       3. A thin-film transistor array substrate comprising:
 a thin-film transistor comprising:
 an active layer, 
 a gate electrode, 
 source and drain electrodes, 
 a first insulation layer disposed between the active layer and the gate electrode, and 
 a second insulation layer disposed between the gate electrode and the source and drain electrodes; 
 
 a pixel electrode disposed on the first and second insulation layers, and connected to one of the source and drain electrodes; 
 a capacitor comprising:
 a first electrode disposed on the same layer as the gate electrode, 
 a second electrode formed of the same material as the pixel electrode, 
 a first protection layer disposed on the second electrode, and 
 a second protection layer disposed on the first protection layer; 
 
 a third insulation layer disposed between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; and 
 a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode. 
 
     
     
       4. The thin-film transistor array substrate of  claim 3 , wherein the second insulation layer is not disposed between the first and second electrodes. 
     
     
       5. The thin-film transistor array substrate of  claim 3 , wherein a thickness of the third insulation layer is thinner than a thickness of the second insulation layer. 
     
     
       6. The thin-film transistor array substrate of  claim 3 , wherein the third insulation layer comprises at least one selected from the group consisting of SiNx, SiO2, ZrO2, TiO2, Ta2O5, and Al2O3. 
     
     
       7. The thin-film transistor array substrate of  claim 3 , wherein the first through third insulation layers are sequentially disposed between the substrate and the pixel electrode in the stated order, wherein refractive indexes of adjacent insulation layers are different from each other. 
     
     
       8. The thin-film transistor array substrate of  claim 3 , wherein the pixel electrode and the third insulation layer have the same etching surface. 
     
     
       9. The thin-film transistor array substrate of  claim 3 , wherein the third insulation layer, the second electrode, and the first protection layer have the same etching surface. 
     
     
       10. The thin-film transistor array substrate of  claim 3 , wherein the second protection layer is formed of the same material as the source and drain electrodes. 
     
     
       11. The thin-film transistor array substrate of  claim 3 , further comprising a pad electrode formed of the same material as the source and drain electrodes. 
     
     
       12. The thin-film transistor array substrate of  claim 3 , wherein a thickness of the third insulation layer is from about 500 Å to about 2000 Å. 
     
     
       13. The thin-film transistor array substrate of  claim 12 , wherein a dielectric constant of the third insulation layer is higher than a dielectric constant of the first insulation layer. 
     
     
       14. The thin-film transistor array substrate of  claim 3 , wherein the pixel electrode comprises a transparent conductive oxide. 
     
     
       15. The thin-film transistor array substrate of  claim 14 , wherein the transparent conductive oxide comprises at least one selected from the group consisting of indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), an indium oxide (In2O3), an indium gallium oxide (IGO), and an aluminum zinc oxide (AZO). 
     
     
       16. The thin-film transistor array substrate of  claim 14 , wherein the pixel electrode further comprises a semi-transmission metal layer. 
     
     
       17. The thin-film transistor array substrate of  claim 16 , wherein the semi-transmission metal layer comprises at least one selected from the group consisting of silver (Ag), aluminum (Al), and alloys thereof 
     
     
       18. The thin-film transistor array substrate of  claim 16 , wherein the semi-transmission metal layer is disposed between layers comprising the transparent conductive oxide. 
     
     
       19. The thin-film transistor array substrate of  claim 3 , wherein the first protection layer comprises at least one selected from the group consisting of Mo, an alloy comprising Mo, Ti, Cu, and Ag. 
     
     
       20. The thin-film transistor array substrate of  claim 19 , wherein a connector of the source or drain electrode connected to the pixel electrode is disposed higher than the pixel electrode, and the first protection layer is disposed between the pixel electrode and the connector. 
     
     
       21. A method of manufacturing the thin-film transistor array substrate according to  claim 3 , the method comprising:
 forming the semiconductor layer on the substrate and forming the active layer of the thin-film transistor by patterning the semiconductor layer; 
 forming the first insulation layer, forming the first conductive layer on the first insulation layer, and then forming the gate electrode of the thin-film transistor and the first electrode of the capacitor by patterning the first conductive layer; 
 forming the second insulation layer and forming an opening in the second insulation layer such that source and drain regions of the active layer and the first electrode are exposed; 
 sequentially forming the third insulation layer, the second conductive layer, and the third conductive layer, and forming the pixel electrode and the second electrode of the capacitor by simultaneously patterning the third insulation layer, the second conductive layer, and the third conductive layer; 
 forming the fourth conductive layer, and forming source and drain electrodes and the second protection layer covering the second electrode by patterning the fourth conductive layer; and 
 forming the fourth insulation layer and removing the fourth insulation layer such that the pixel electrode is exposed. 
 
     
     
       22. The method of  claim 21 , wherein ion impurities are doped on the source and drain regions. 
     
     
       23. The method of  claim 21 , further comprising performing a first etching process by etching the third insulation layer, and performing a second etching process by etching the second and third conductive layers. 
     
     
       24. The method of  claim 21 , wherein the third conductive layer remaining on the pixel electrode is removed. 
     
     
       25. The method of  claim 21 , wherein the fourth conductive layer is used to further form a pad electrode. 
     
     
       26. The method of  claim 21 , wherein the third insulation layer is thinner than the second insulation layer. 
     
     
       27. The method of  claim 21 , wherein the third insulation layer is formed of a material having a higher dielectric constant than the first insulation layer. 
     
     
       28. The method of  claim 21 , wherein the second conductive layer is formed of a layer comprising a transparent conductive oxide. 
     
     
       29. The method of  claim 28 , wherein the second conductive layer is formed to include a first layer comprising a transparent conductive oxide, a second layer comprising a semi-transmission metal, and a third layer comprising a transparent conductive oxide.