Method to increase breakdown voltage of semiconductor devices

Abstract

Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.

What is claimed: 
     
       1. A semiconductor device comprising:
 a substrate; 
 a group III nitride semi-insulating buffer layer overlying the substrate, wherein the group III nitride layer comprises Al x In y Ga 1-x-y N, wherein 0≦x≦1, 0≦y≦1 and 0<x+y≦1; 
 a group III nitride channel layer overlying the buffer layer, wherein the group III nitride layer comprises Al x In y Ga 1-x-y N, wherein 0≦x≦1, 0≦y≦1 and 0<x+y≦1; 
 a group III nitride barrier layer overlying the channel layer, wherein the group III nitride layer comprises Al x In y Ga 1-x-y N, wherein 0≦x≦1, 0≦y≦1 and 0<x+y≦1; 
 a drain electrode, a source electrode, and a gate overlying the group III nitride barrier layer; 
 a high dielectric strength insulating material deposited over at least a portion of one of the source electrode, the drain electrode or the gate; and 
 a multi stack drain field plate formed above said high dielectric strength insulating material, and connected to said drain electrode. 
 
     
     
       2. The semiconductor device as in  claim 1 , wherein the high dielectric strength insulating material has a dielectric strength greater than air. 
     
     
       3. The semiconductor device as in  claim 1 , wherein said high dielectric strength insulating material comprises of the following; silicon dioxide, silicon nitride, benzocyclobutene, aluminium nitride, aluminum galium nitride, galium nitride, boron nitride, silicon carbide, diamond, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, scandium oxide, polytetrafluoroethylene, perfluoroalkoxy, fluorinated ethylene propylene, polystyrene, polyoxybenzylmethylenglycolanhydride, or combinations thereof. 
     
     
       4. The semiconductor device as in  claim 1 , wherein the high dielectric strength insulating material is deposited on a top surface of the heterostructure field effect transistor between the drain electrode and the gate. 
     
     
       5. The semiconductor device as in  claim 1 , wherein the high dielectric strength insulating material is deposited on a top surface of the heterostructure field effect transistor between the source electrode and the gate. 
     
     
       6. The semiconductor device as in  claim 1 , wherein the high dielectric strength insulating material having a dielectric strength greater than 3 MV/m but less than 100 MV/m. 
     
     
       7. The semiconductor device as in  claim 1 , further comprising:
 a field plate formed above said high dielectric strength insulating material film, and connected to said source electrode or said gate electrode. 
 
     
     
       8. The semiconductor device as in  claim 1 , further comprising:
 a drain field plate formed above said high dielectric strength insulating material, and connected to said drain electrode. 
 
     
     
       9. The semiconductor device as in  claim 1 , further comprising:
 multi stack field plate formed above said high dielectric strength insulating material film, and connected to said source electrode or said gate electrode. 
 
     
     
       10. The semiconductor device as in  claim 1 , wherein the breakdown voltage is between about 300_Y and 100 KV.