Delay lines, amplifier systems, transconductance compensating systems and methods of compensating

Abstract

Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

We claim: 
     
       1. A delay line, comprising:
 a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit; and 
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes, wherein each of the delay stages is further configured to use the bias signal to maintain the gain of the respective delay stage at a substantially unity gain at a particular magnitude of an input signal applied to the respective delay stage as a transconductance of the at least one in transistor in the respective delay stage changes, and wherein each of the delay stages is further configured to have a gain of greater than unit for an input signal provided to the respective delay stage having a magnitude that is less than the particular magnitude, and a gain of less than unity for an input signal provided to the respective delay stage having a magnitude that is greater than the particular magnitude. 
 
     
     
       2. The delay line of  claim 1  wherein each of the delay stages comprises:
 first and second input transistors having respective sources coupled to each other, respective drains coupled to a first supply voltage node through respective loads, and respective gates coupled to receive respective differential input signal nodes; and 
 a current sink coupling the sources of the first and second input transistors to a second supply voltage node. 
 
     
     
       3. The delay line of  claim 2  wherein the current sink comprises a current sink transistor having a drain coupled to the sources of the first and second input transistors, a source coupled to the second supply voltage node, and a gate coupled to the output node of the compensating circuit. 
     
     
       4. A delay line, comprising:
 a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of transconductance of the at least one transistor in the compensating circuit, the compensating circuit further comprising first and second input transistors having respective sources coupled to each other, respective drains coupled to the first supply voltage node through respective loads, and respective gates, the gate of the first input transistor being coupled to the drain of the second input transistor, and the gate of the second input transistor being coupled to the drain of the first input transistor; 
 a current sink transistor having a drain coupled to the sources of the first and second input transistors, a source coupled to the second supply voltage node, and a gate coupled to the output node of the compensating circuit; and 
 a comparison circuit configured to compare a reference voltage with a voltage corresponding to a difference in the magnitude of a first voltage at the drain of the first input transistor and a second voltage at the drain of the second input transistor, the comparison circuit being configured to provide the bias signal as a function of the comparison and to provide the bias signal to the output node of the compensating circuit; and 
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes, the delay stages further comprising first and second input transistors having respective sources coupled to each other, respective drains coupled to a first supply voltage node through respective loads, and respective gates coupled to receive respective differential input signal nodes, and a current sink coupling the sources of the first and second input transistors to a second supply voltage node, wherein the current sink comprises a current sink transistor having a drain coupled to the sources of the first and second input transistors, a source coupled to the second supply voltage node, and a gate coupled to the output node of the compensating circuit. 
 
     
     
       5. The delay line of  claim 4  wherein the comparison circuit comprises:
 a differential-to-single converter having first and second input nodes coupled to the drains of the first and second input transistors, respectively, the differential-to-single converter being configured to provide an output signal at an output node having a magnitude corresponding to the difference in the magnitude of the first voltage at the drain of the first input transistor and the second voltage at the drain of the second input transistor, and 
 a differential amplifier having a first input coupled to the output node of the differential-to-single converter, a second input coupled to receive the reference voltage, the differential amplifier being configured to provide the bias voltage and to provide the bias voltage to the output node of the compensating circuit. 
 
     
     
       6. The delay line of  claim 5  wherein the differential amplifier is configured to adjust the current drawn by the current sink transistor to adjust a transconductance of the first and second input transistors. 
     
     
       7. The delay line of  claim 4  wherein the first and second input transistors of the compensating circuit have substantially the same electrical characteristics as each other and substantially the same electrical characteristics as the first and second input transistors of each of the delay stages. 
     
     
       8. The delay line of  claim 4  wherein the current sink transistor of the compensating circuit has substantially the same electrical characteristics as the current sink transistor in each of the delay stages. 
     
     
       9. A delay line, comprising:
 a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit; 
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes; and 
 a start circuit configured to initially provide an input signal to the compensating circuit. 
 
     
     
       10. A delay line comprising:
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and configured to receive a control signal, and each of the delay stages configured to provide a gain of the respective delay stage in accordance with the control signal to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes; and 
 a compensating circuit configured to generate the control signal, wherein the compensating circuit comprises a bias voltage generator having at least one transistor having same electrical characteristics as the at least one input transistor, wherein the at least one transistor of the bias voltage generator comprises a first and second transistor, each having the same electrical characteristics as the at least one input transistor, and wherein the first and second transistors have respective first source/drains coupled to each other, and wherein the control signal has a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit. 
 
     
     
       11. The delay line of  claim 10 , wherein the first and second transistors further have respective second source/drains coupled to a supply voltage through respective loads. 
     
     
       12. A delay line comprising:
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and configured to receive a control signal, and each of the delay stages configured to provide a gain of the respective delay stage in accordance with the control signal; and 
 a compensating circuit configured to generate the control signal, wherein the compensating circuit comprises a bias voltage generator having at least one transistor having same electrical characteristics as the at least one input transistor, wherein the at least one transistor of the bias voltage generator comprises a first and second transistor, each having the same electrical characteristics as the at least one input transistor, wherein the first and second transistors have respective first source/drains coupled to each other, wherein the first and second transistors further have respective gates, a gate of the first transistor coupled to a second source/drain of the second transistor, and a gate of the second transistor coupled to a second source/drain of the first transistor, and wherein the control signal has a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit. 
 
     
     
       13. The delay line of  claim 10 , wherein the bias voltage generator further comprises a third transistor having a source/drain coupled to the first source/drains of the first and second transistors, and a gate coupled to an output of the compensating circuit configured to provide the control signal. 
     
     
       14. The delay line of  claim 13 , wherein the plurality of delay stages further include respective current sink transistors, and wherein the third transistor has same electrical characteristics as the respective current sink transistors. 
     
     
       15. A delay line comprising:
 a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor, wherein the first and second transistors further have respective second source/drains coupled to a supply voltage through respective loads, and configured to receive a control signal, and each of the delay stages configured to provide a gain of the respective delay stage in accordance with the control signal; and 
 a compensating circuit configured to generate the control signal, wherein the compensating circuit comprises a bias voltage generator having at least one transistor having same electrical characteristics as the at least one input transistor, wherein the at least one transistor of the bias voltage generator comprises a first and second transistor, each having the same electrical characteristics as the at least one input transistor, and wherein the first and second transistors have respective first source/drains coupled to each other, and wherein the control signal has a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit, wherein the compensating circuit further comprises a differential-to-single converter, the differential-to-single converter having inputs coupled to the second source/drains and the differential-to-single converter configured to convert a differential signal received at the inputs to a single-ended signal at an output. 
 
     
     
       16. The delay line of  claim 15 , wherein the compensating circuit further comprises a comparison circuit, the comparison circuit configured to receive the single-ended signal and a reference signal and provide an output to the bias voltage generator based on a comparison between the single-ended signal and the reference signal. 
     
     
       17. The delay line of  claim 16 , wherein the reference signal corresponds with a desired magnitude for signal propagation through the delay line.