Computing device mismatch variation contributions

Abstract

A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.

What is claimed is: 
     
       1. A computer-implemented method for analyzing circuit performance variations, comprising:
 using a computer, allocating circuit performance variation by weighting individual mismatch parameters in a multiple linear regression model; 
 summarizing device performance variation contributions by summing all weighted individual mismatch parameter values corresponding to the devices in a circuit design; 
 ranking the device performance variation contributions; and 
 identifying and outputting at least one influential device according to device performance variation contribution rank order. 
 
     
     
       2. The method of  claim 1  wherein the weighting further comprises assigning circuit performance variation contributions to individual mismatch parameters with an ordered metric. 
     
     
       3. The method of  claim 2  wherein the assigning further comprises evaluating a coefficient of determination for each individual mismatch parameter according to its marginal influence over the influences of all previously considered individual mismatch parameters. 
     
     
       4. The method of  claim 1  wherein the allocating further comprises approximating the weighting by optimizing selected sparse factors against limited sample data. 
     
     
       5. The method of  claim 4  wherein an orthogonal matching pursuit performs the optimizing. 
     
     
       6. The method of  claim 1  further comprising performing a statistical sensitivity analysis on selected influential devices. 
     
     
       7. The method of  claim 1  further comprising increasing at least one of circuit performance, circuit yield, and circuit design robustness. 
     
     
       8. A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for allocating circuit variance into device mismatch parameters, the method comprising:
 allocating circuit performance variation by weighting individual mismatch parameters in a multiple linear regression model; 
 summarizing device performance variation contributions by summing all weighted individual mismatch parameter values corresponding to the devices in a circuit design; 
 ranking the device performance variation contributions; and 
 identifying and outputting at least one influential device according to device performance variation contribution rank order. 
 
     
     
       9. The medium of  claim 8  wherein the weighting further comprises assigning circuit performance variation contributions to individual mismatch parameters with an ordered metric. 
     
     
       10. The medium of  claim 9  wherein the assigning further comprises evaluating a coefficient of determination for each individual mismatch parameter according to its marginal influence over the influences of all previously considered individual mismatch parameters. 
     
     
       11. The medium of  claim 8  wherein the allocating further comprises approximating the weighting by optimizing selected sparse factors against limited sample data. 
     
     
       12. The medium of  claim 11  wherein an orthogonal matching pursuit performs the optimizing. 
     
     
       13. The medium of  claim 8  wherein the method further comprises performing a statistical sensitivity analysis on selected influential devices. 
     
     
       14. The medium of  claim 8  wherein the method further comprises increasing at least one of circuit performance, circuit yield, and circuit design robustness. 
     
     
       15. A system for allocating circuit variance into device mismatch parameters, the system comprising:
 a non-transitory computer-readable medium to store a circuit design; 
 a processor executing instructions to: 
 allocate circuit performance variation by weighting individual mismatch parameters in a multiple linear regression model; 
 summarize device performance variation contributions by summing all weighted individual mismatch parameter values corresponding to the devices in a circuit design; 
 rank the device performance variation contributions; and 
 identify and output at least one influential device according to device performance variation contribution rank order. 
 
     
     
       16. The system of  claim 15  wherein the weighting further comprises assigning circuit performance variation contributions to individual mismatch parameters with an ordered metric. 
     
     
       17. The system of  claim 16  wherein the assigning further comprises evaluating a coefficient of determination for each individual mismatch parameter according to its marginal influence over the influences of all previously considered individual mismatch parameters. 
     
     
       18. The system of  claim 15  wherein the allocating further comprises approximating the weighting by optimizing selected sparse factors against limited sample data. 
     
     
       19. The system of  claim 18  wherein an orthogonal matching pursuit performs the optimizing. 
     
     
       20. The system of  claim 15  wherein the processor further executes instructions to perform a statistical sensitivity analysis on selected influential devices.