Low temperature BEOL compatible diode having high voltage margins for use in large arrays of electronic components

Abstract

A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×10 6 A/cm 2 . This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

The invention claimed is: 
     
       1. A device, comprising:
 (a) a bit line; 
 (b) a M a X b Y 2  layer, wherein
 a=0.4 to 1.2, b=0.8 to 1.2, 
 M is selected from the group consisting of Cu, Ag, Li and Zn, 
 X is selected from the group consisting of Cr, Mo and W, and 
 Y is selected from the group consisting of Se, S, O and Te; 
 
 (c) a memory element; 
 (d) a word line, and 
 wherein the M a X b Y 2  layer and the memory element are: (i) sandwiched between the bit line and the word line, and (ii) in electrical series with the word and bit lines. 
 
     
     
       2. The device of  claim 1 , wherein the M a X b Y 2  layer is Cu a Cr b S 2 , where a=0.4 to 1.2 and b=0.8 to 1.2. 
     
     
       3. The device of  claim 2 , wherein the M a X b Y 2  layer is Cu 0.24±0.005 Cr 0.26±0.005 S 0.5±0.01 . 
     
     
       4. The device of  claim 2 , wherein the M a X b Y 2  layer is Cu 0.24±0.005 Cr 0.26±0.005 Se 0.5±0.01 . 
     
     
       5. The device of  claim 1 , further including conducting layers contacting opposite sides of the M a X b Y 2  material. 
     
     
       6. The device of  claim 5 , wherein at least one of the conducting layers is inert. 
     
     
       7. The device of  claim 5 , wherein at least one of the conducting layers includes Cu 3 Ge. 
     
     
       8. The device of  claim 1 , wherein the device operates reliably at a current density greater than 5×10 6  A/cm 2 . 
     
     
       9. The device of  claim 1 , wherein the device has a voltage margin greater than 1V. 
     
     
       10. A crosspoint memory array comprising an array of the devices of  claim 1 . 
     
     
       11. A method, comprising applying voltage to the array of  claim 10 , thereby changing the state of one of the memory elements. 
     
     
       12. The method of  claim 11 , further comprising reading out the state of said one of the memory elements. 
     
     
       13. The method of  claim 12 , wherein the state that is read out is the resistance of one of the memory elements. 
     
     
       14. The device of  claim 1 , wherein the device is further sandwiched between dielectrics on its side. 
     
     
       15. The device of  claim 1 , wherein the device is part of any of, or a combination of, the following structures: a mushroom structure, a recessed mushroom structure, a pillar cell, a lithographic pore structure, a sublithographic pore structure, and a ring-shaped cell structure. 
     
     
       16. The device of  claim 1 , wherein said memory element is any of the following: phase change memory (PCM), resistive RAM (RRAM), or magnetoresistive RAM (MRAM). 
     
     
       17. A device, comprising:
 (a) a bit line; 
 (b) a Cu a Cr b S c  layer sandwiched by top and bottom conductive layers, wherein 
 a=0.24±0.005, b=0.26±0.005, and c=0.50±0.01; 
 (c) a memory element; 
 (d) a word line, and 
 wherein the Cu a Cr b S c  layer and the memory element are: (i) sandwiched between the bit line and the word line, and (ii) in electrical series with the word and bit lines. 
 
     
     
       18. The device of  claim 17 , wherein the device operates reliably at a current density greater than 5×10 6  A/cm 2 . 
     
     
       19. The device of  claim 17 , wherein the device has a voltage margin greater than 1V. 
     
     
       20. A crosspoint memory array comprising an array of the devices of  claim 17 . 
     
     
       21. A method, comprising applying voltage to the array of  claim 20 , thereby changing the state of one of the memory elements. 
     
     
       22. The method of  claim 21 , further comprising reading out the state of said one of the memory elements. 
     
     
       23. The method of  claim 22 , wherein the state that is read out is the resistance of one of the memory elements. 
     
     
       24. The device of  claim 17 , wherein the device is part of any of, or a combination of, the following structures: a mushroom structure, a recessed mushroom structure, a pillar cell, a lithographic pore structure, a sublithographic pore structure, and a ring-shaped cell structure. 
     
     
       25. The device of  claim 17 , wherein said memory element is any of the following: phase change memory (PCM), resistive RAM (RRAM), or magnetoresistive RAM (MRAM). 
     
     
       26. A device, comprising:
 (a) a bit line; 
 (b) a Cu a Cr b Se c  layer sandwiched by top and bottom conductive layers, wherein 
 a=0.24±0.005, b=0.26±0.005, and c=0.50±0.01; 
 (c) a memory element; 
 (d) a word line, and 
 wherein the Cu a Cr b Se c  layer and the memory element are: (i) sandwiched between the bit line and the word line, and (ii) in electrical series with the word and bit lines. 
 
     
     
       27. The device of  claim 26 , wherein the device operates reliably at a current density greater than 5×10 6  A/cm 2 . 
     
     
       28. The device of  claim 26 , wherein the device has a voltage margin greater than 1V. 
     
     
       29. A crosspoint memory array comprising an array of the devices of  claim 26 . 
     
     
       30. The device of  claim 26 , wherein said memory element is any of the following: phase change memory (PCM), resistive RAM (RRAM), or magnetoresistive RAM (MRAM).