P
US8912069B2ActiveUtilityPatentIndex 63

Semiconductor device with STI and method for manufacturing the semiconductor device

Assignee: FUJITSU SEMICONDUCTOR LTDPriority: Jun 30, 2006Filed: Jul 15, 2013Granted: Dec 16, 2014
Est. expiryJun 30, 2026(expired)· nominal 20-yr term from priority
Inventors:EMA TAIJIMIZUTANI KAZUHIRO
H10W 10/0145H10W 10/17H10W 10/011H10W 10/10H10B 41/40H10D 30/681H10D 30/6894H10D 30/68H01L 29/42336H01L 27/11536H01L 29/788H01L 27/11546H01L 29/7881H01L 27/105H01L 21/762H01L 27/11526H01L 21/76232H01L 27/11575H01L 27/11548H10B 41/49H10B 41/44H10B 43/50H10B 41/50
63
PatentIndex Score
3
Cited by
57
References
6
Claims

Abstract

A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A method for manufacturing a semiconductor device comprising:
 forming a mask pattern on a semiconductor substrate that includes a memory cell area and a logic circuit area; 
 forming an isolation trench, that defines a first active region of the semiconductor substrate in the memory cell area and a second active region of the semiconductor substrate in the logic circuit area, in the semiconductor substrate, the mask pattern being located on the first active region and the second active region; 
 forming an isolation material film in the isolation trench; 
 forming a resist pattern that covers the isolation material film in the logic circuit area; 
 implanting ions to the first active region using the resist pattern as a mask; 
 removing part of the isolation material film in the memory cell area using the resist pattern as a mask; and 
 removing the resist pattern and the mask pattern after the implanting ions and the removing part of the isolation material film. 
 
     
     
       2. The method for manufacturing a semiconductor device according to  claim 1 ,
 wherein the forming the isolation trench is performed using the mask pattern as a mask. 
 
     
     
       3. The method for manufacturing a semiconductor device according to  claim 2 , wherein the forming the isolation trench is performed by dry etching using the mask pattern as a mask. 
     
     
       4. The method for manufacturing a semiconductor device according to  claim 1 , wherein in area subjected to the removing part of the isolation material film, the isolation material film in the memory cell area remains and becomes thinner than the isolation material film in the logic circuit area. 
     
     
       5. The method for manufacturing a semiconductor device according to  claim 1 , wherein the mask pattern includes silicon nitride. 
     
     
       6. The method for manufacturing a semiconductor device according to  claim 1 , wherein the implanting ions to the first active region is done through the mask pattern.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.