Decoding method and apparatus for non-binary, low-density, parity check codes

Abstract

Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute d c output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.

The invention claimed is: 
     
       1. A decoding method to compute d c  output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space, comprising:
 converting reliability vector messages of d c  input vectors of a NBPC equation decoding unit to reliability vector messages of a delta domain, computed in logarithm-form with a value of maximum reliability as a reference for the corresponding conversion of an input vector to the delta domain reliability vector; 
 determining one or more minimum values among each and every collection of the delta domain input vector entries corresponding respectively to each and every possible non-zero state of the NB space; 
 storing in a final state (FS) storage, for respectively each and every possible non-zero state of the NB space, one or more minimum values and indicia of minimum values locations in an extra compressed state, called FS as above; 
 computing a FS reliability, for each and every possible non-zero state of the NB space, as a result of a selection either of the minimum value of the considered non-zero state of the NB space, or of a combination sum of at least two minimum values stored in the FS storage; 
 setting the FS reliability for the zero state of the NB space as zero; and 
 computing the d c  output vectors of reliabilities in a delta domain representation, based on the minimum values and indicia of minimum values locations stored in the FS storage and the FS reliabilities. 
 
     
     
       2. The decoding method of  claim 1 , further comprising storing FS reliabilities in the FS storage and accessing them from FS storage to be used for the computation of the dc output vectors of reliabilities in the delta domain representation. 
     
     
       3. The decoding method of  claim 1 , wherein the computation of the FS reliabilities for each and every non-zero-state of the NB space uses the selection of one minimum or the combination sum of at least two minimum values, while the d c  output vectors of reliabilities in the delta domain representation are computed using an equal or larger number of minimum values compared to the number of minimum values used for the computation of the FS reliabilities. 
     
     
       4. The decoding method of  claim 1 , wherein the computation of the final state reliabilities for each and every non-zero-state of the NB space uses only one minimum, while the d c  output vectors of reliabilities in the delta domain representation are computed using two or more minimum values stored in the FS storage. 
     
     
       5. The decoding method of  claim 1 , further comprising storing the minimum values in the dc output vectors of reliabilities in the delta domain representation, in addition to storing the minimum values in the FS storage. 
     
     
       6. The decoding method of  claim 1 , further comprising computing the d c  output vectors of reliabilities of a check-node in the delta domain representation can be scheduled any time after the availability of compressed state of that check-node. 
     
     
       7. The decoding method of  claim 1 , further comprising summing the check-node units output message and check-node units input message to produce a total reliability message. 
     
     
       8. The decoding method of  claim 1 , further comprising generating and computing the d c  output vectors of reliabilities in the delta domain representation belonging to previous iteration, during current iteration, based on the minimum values and indicia of minimum values locations belonging to previous iteration that are stored in the FS storage. 
     
     
       9. The decoding method of  claim 1 , further comprising delaying a check-node units input message in a memory until a check-node unit output message is generated. 
     
     
       10. A decoding apparatus comprising NB-LDPC codes with software instructions programmed into a non-transient memory of a computer controller, including an input, output, and microprocessor, operably running a decoding calculation and steps for NB-LDPC codes, the software including an EMS calculation and logic in a particular representation called trellis arrangement or T-EMS, wherein such a decoding apparatus for decoding d c -sized vector messages comprises a check-node unit (CNU) architecture with two units in connection for each CNU, a Min-finder unit which builds the delta domain trellis representation which contains the minimum values and computes the FS and a V-select unit which computes extra compressed values and extrinsic V messages, such units further comprise:
 (a) in the Min-finder unit:
 a series of parallel entries for respective incoming vector messages; 
 a series of registers to store indicia of each incoming message in connection with the respective entry; 
 a series of substrators to transform each message to the delta domain in connection with the respective register; 
 a Min-finder tree to select minimum values and indicia from transformed d c -sized vectors; and 
 
 (b) in the V-select unit:
 an extra-out block to generate FS reliabilities, also called syndrome reliabilities, based on the values stored in the FS registers; 
 a d c -out block composed of subtractors to fill all the d c  extrinsic messages with the syndrome values and the stored configurations; and 
 a message de-map block composed of substrators to transform the messages back to output messages of the normal domain. 
 
 
     
     
       11. The decoding apparatus of  claim 10 , wherein:
 the minimum values are stored in final states registers; 
 the extra-out block includes adders and multiplexers; and 
 the configuration associated to each syndrome value and indicia of minimum values are stored in temporary registers of the extra-out block. 
 
     
     
       12. The decoding apparatus of  claim 10 , further comprising a block parallel layered decoder architecture comprises one CNU and a second V-select unit to compute the FS reliabilities values and the extrinsic V messages, the V-select unit including an extra-out block, a d c -out block and a de-map block. 
     
     
       13. The decoding apparatus of  claim 12 , wherein the extra-out block of the second V-select unit is removed and the FS reliabilities values are also stored in final state storage.