Single poly electrically erasable programmable read only memory (single poly EEPROM) device

Abstract

A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.

What is claimed is: 
     
       1. A single poly electrically erasable programmable read only memory (single poly EEPROM) device, comprising:
 a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; 
 a P-well region formed in a portion of the P-type semiconductor layer; 
 a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; 
 an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; 
 a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and 
 a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation, wherein the control gate does not physically contact the trench isolation. 
 
     
     
       2. The single poly EEPROM device as claimed in  claim 1 , wherein the SOI substrate further comprises a semiconductor layer, and the insulating layer and the P-type semiconductor are sequentially formed over the semiconductor layer. 
     
     
       3. The single poly EEPROM device as claimed in  claim 1 , wherein the trench isolation encircles the P-type well region, and a bottom surface of the trench isolation physically contacts the insulating layer. 
     
     
       4. The single poly EEPROM device as claimed in  claim 1 , further comprising a field oxide disposed over a portion of the P-type semiconductor layer in the P-type well region to encircle the NMOS transistor and to isolate the P+ doping region from the NMOS transistor. 
     
     
       5. The single poly EEPROM device as claimed in  claim 4 , wherein the P+ doping region encircles the field oxide. 
     
     
       6. The single poly EEPROM device as claimed in  claim 4 , wherein the NMOS transistor comprises:
 a gate dielectric layer disposed over a portion of the P-type semiconductor layer in the P well region; 
 a polysilicon layer disposed over the gate dielectric layer; and 
 an N+ doping region disposed in the P-type semiconductor layer on opposite two sides of the polysilicon layer. 
 
     
     
       7. The single poly EEPROM device as claimed in  claim 4 , wherein the gate dielectric layer and the polysilicon layer of the NMOS transistor further extend over a portion of the control gate. 
     
     
       8. The single poly EEPROM device as claimed in  claim 1 , wherein the control gate is an N-well region formed in another portion of the P-type semiconductor layer. 
     
     
       9. The single poly EEPROM device as claimed in  claim 8 , further comprising an N+ doping region formed in the N-well region. 
     
     
       10. The single poly EEPROM device as claimed in  claim 9 , further comprising a field oxide disposed over another portion of the P-type semiconductor layer in the P well region, surrounding the N+ doping region and the N-well region. 
     
     
       11. The single poly EEPROM device as claimed in  claim 1 , wherein a first positive voltage is applied to the control gate, a second positive voltage is applied to a drain region of the NMOS transistor, and a source region of the NMOS transistor and the P-well region are grounded to thereby program the single poly EEPROM device. 
     
     
       12. The single poly EEPROM device as claimed in  claim 11 , wherein the first positive voltage is of about 6-7 V, and the second positive voltage is of about 6-7 V, and the program operation is achieved by hot electron injection effects. 
     
     
       13. The single poly EEPROM device as claimed in  claim 1 , wherein a positive voltage is applied to the control gate, a drain region of the NMOS transistor is floated, and a source region of the NMOS transistor and the P-well region are grounded to thereby program the single poly EEPROM device. 
     
     
       14. The single poly EEPROM device as claimed in  claim 13  wherein the positive voltage is of about 12-14 V and the program operation is achieved by Fowler-Nordheim tunneling effects. 
     
     
       15. The single poly EEPROM device as claimed in  claim 1 , wherein a first positive voltage is applied to the P well region, a second positive voltage is applied to a source region of the NMOS transistor, a drain region of the NMOS transistor is floated, and the control gate is grounded to thereby erase the single poly EEPROM device. 
     
     
       16. The single poly EEPROM device as claimed in  claim 15 , wherein the first positive voltage is about 12-14 V, and the second positive voltage is about 12-14 V, and the erase operation is achieved by Fowler-Nordheim tunneling effects.