Heterostructure power transistor with AlSiN passivation layer

Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

We claim: 
     
       1. A heterostructure power transistor comprising:
 a first active layer, 
 a second active layer disposed on the first active layer, a two-dimensional electron gas layer forming between the first and second active layers; 
 a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) disposed on the second active layer; 
 an AlN layer disposed above the passivation/gate dielectric layer; 
 a gate; 
 a second gate dielectric layer disposed on the AlN layer, the gate being disposed above the second gate dielectric layer; 
 first and second ohmic contacts that electrically connect to the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts. 
 
     
     
       2. The heterostructure power transistor of  claim 1  wherein the second gate dielectric layer comprises aluminum oxide (Al 2 O 3 ). 
     
     
       3. The heterostructure power transistor of  claim 1  further comprising an upper passivation layer disposed over the second gate dielectric layer, the gate extending vertically through the upper passivation layer to contact the second gate dielectric layer. 
     
     
       4. The heterostructure power transistor of  claim 1  wherein the passivation/gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the second thickness being larger than the first thickness. 
     
     
       5. The heterostructure power transistor of  claim 1  wherein the first and second ohmic contacts extend vertically through the second gate dielectric layer and the passivation/gate dielectric layer. 
     
     
       6. The heterostructure power transistor of  claim 3  wherein the first and second ohmic contacts extend vertically through the upper passivation layer, the second gate dielectric layer, and the passivation/gate dielectric layer. 
     
     
       7. The heterostructure power transistor of  claim 1  wherein the passivation/gate dielectric layer has a first thickness in a range of about 1-5 nanometers thick. 
     
     
       8. The heterostructure power transistor of  claim 1  wherein the second gate dielectric has a second thickness in a range of about 10-20 nanometers thick. 
     
     
       9. The heterostructure power transistor of  claim 1  wherein the first and second ohmic contacts respectively comprise source and drain ohmic contacts. 
     
     
       10. The heterostructure power transistor of  claim 3  wherein the upper passivation layer comprises SiN. 
     
     
       11. The heterostructure power transistor according to  claim 1  wherein the first active layer comprises gallium nitride (GaN). 
     
     
       12. The heterostructure power transistor of  claim 1  wherein the second active layer comprises aluminum gallium nitride (AlGaN). 
     
     
       13. The heterostructure power transistor of  claim 1  wherein the first and second active layers are defined as an isolated mesa. 
     
     
       14. A method of fabricating a heterostructure semiconductor device comprising:
 forming a first active layer on a substrate; 
 forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween; 
 forming a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) on the second active layer, the passivation/gate dielectric layer having a first thickness, wherein the forming of the passivation/gate dielectric layer comprises growing in-situ with the AlSiN layer an AlN layer on top of the AlSiN layer;
 forming a second gate dielectric layer of aluminum oxide over the passivation/gate dielectric layer using the AlN layer as a seed layer; 
 forming first and second ohmic contacts that each extend vertically through the passivationfgate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer; and 
 forming a gate at a lateral position between the first and second ohmic contacts. 
 
 
     
     
       15. The method of  claim 14  wherein the second gate dielectric layer has a second thickness greater than the first thickness. 
     
     
       16. The method of  claim 15  further comprising depositing an upper passivation layer over the second gate dielectric layer. 
     
     
       17. The method of  claim 14  wherein the first active layer comprises gallium nitride. 
     
     
       18. The method of  claim 14  wherein the second active layer comprises aluminum gallium nitride. 
     
     
       19. The method of  claim 14  wherein the passivation/gate dielectric layer is formed in-situ with the first and second active layers. 
     
     
       20. The method of  claim 14  wherein forming the passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) comprises growing the aluminum silicon nitride (AlSiN) with an integrated nitrogen composition that is at stoichiometry between Si 3 N 4  and AlN. 
     
     
       21. The method of  claim 14  wherein forming the passivationfgate dielectric layer comprising aluminum silicon nitride (AlSiN) comprises forming the aluminum silicon nitride (AlSiN) with substantially 5-10% of aluminum (Al) to silicon nitride (SiN). 
     
     
       22. The heterostructure power transistor of  claim 1 , wherein the aluminum silicon nitride (AlSiN) has an integrated nitrogen composition that is at stoichiometry between Si 3 N 4  and AlN. 
     
     
       23. The heterostructure power transistor of  claim 1  wherein the aluminum silicon nitride (AlSiN) has substantially 5-10% of aluminum (Al) to silicon nitride (SiN).