Memory cell floating gate replacement

Abstract

A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.

The invention claimed is: 
     
       1. A method of forming a NAND flash memory integrated circuit comprising:
 forming a first polysilicon layer overlying a gate dielectric layer; 
 forming a first dielectric layer overlying the first polysilicon layer; 
 forming a second polysilicon layer overlying the first dielectric layer; 
 removing the second polysilicon layer in an array area using the first dielectric layer as an etch stop, while maintaining the second polysilicon layer in a peripheral area; 
 depositing a second dielectric layer and a third polysilicon layer to replace the second polysilicon layer in the array area; 
 forming a floating gate in the array area from a portion of the first polysilicon layer and a portion of the third polysilicon layer connected through a portion of the second dielectric layer; and 
 forming a transistor gate in the peripheral area from a portion of the first polysilicon layer and a portion of the second polysilicon layer connected through a portion of the first dielectric layer. 
 
     
     
       2. The method of  claim 1  wherein the first polysilicon layer and the second polysilicon layer are of a first type and the third polysilicon layer is of a second type. 
     
     
       3. The method of  claim 2  wherein the first type is N-type and the second type is P-type. 
     
     
       4. The method of  claim 3  wherein the third polysilicon layer is in-situ doped with Boron and the second dielectric layer forms a barrier to Boron diffusion. 
     
     
       5. The method of  claim 4  wherein the second dielectric layer is formed of Silicon Nitride. 
     
     
       6. The method of  claim 1  wherein the first dielectric layer is removed along with the second polysilicon layer in the array area prior to depositing the second dielectric layer and the third polysilicon layer. 
     
     
       7. The method of  claim 1  wherein the first dielectric layer is maintained in the array area when the second polysilicon layer is removed, and the second dielectric layer is deposited directly on the first dielectric layer in the array area. 
     
     
       8. The method of  claim 1  wherein the first dielectric layer is Silicon dioxide. 
     
     
       9. The method of  claim 8  wherein the first dielectric layer has a thickness that is sufficiently small that the first polysilicon layer and the second polysilicon layer are substantially electrically connected. 
     
     
       10. A method of forming a NAND flash memory integrated circuit comprising:
 forming a gate dielectric layer on a surface of a substrate; 
 forming a first in-situ doped N-type polysilicon layer on the gate dielectric layer; 
 forming a Silicon dioxide layer on the first in-situ doped N-type polysilicon layer; 
 forming a second in-situ doped N-type polysilicon layer on the first dielectric layer; 
 removing the second in-situ doped N-type polysilicon layer in an array area by selective etching using the Silicon dioxide layer as an etch stop, while maintaining the second in-situ doped N-type polysilicon layer in a peripheral area using an etch mask; 
 depositing a barrier layer and an in-situ doped P-type polysilicon layer to replace the second in-situ doped N-type polysilicon layer in the array area; 
 forming a floating gate in the array area from a portion of the first in-situ doped N-type polysilicon layer and a portion of the in-situ doped P-type polysilicon layer that are electrically connected through a portion of the barrier layer; and 
 forming a peripheral transistor gate in the peripheral area from a portion of the first in-situ doped N-type polysilicon layer and a portion of the second in-situ doped N-type polysilicon layer that are electrically connected through a portion of the dielectric layer. 
 
     
     
       11. The method of  claim 10  wherein the dielectric layer is a thin Silicon dioxide layer. 
     
     
       12. The method of  claim 10  wherein the barrier layer is a thin Silicon nitride layer. 
     
     
       13. The method of  claim 10  wherein the in-situ doped P-type polysilicon layer is a Boron doped layer and the barrier layer provides a barrier to Boron diffusion.