Emulation of an input/output advanced programmable interrupt controller

Abstract

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

What is claimed is: 
     
       1. An apparatus comprising:
 a first interrupt controller having a first programming model; and 
 emulation logic to emulate a second interrupt controller having a second programming model different from the first programming model, wherein the second programming model is an Advanced Programmable Interrupt Controller programming model, and to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. 
 
     
     
       2. The apparatus of  claim 1 , wherein the second interrupt controller is an input/output Advanced Programmable Interrupt Controller. 
     
     
       3. The apparatus of  claim 1 , wherein the first interrupt controller includes a plurality of mask indicators, and the emulation logic is to mask one of the plurality of interrupt requests to the first interrupt controller using one of the plurality of mask indicators. 
     
     
       4. The apparatus of  claim 1 , further comprising a random access memory to store information corresponding to contents of the register set of the second interrupt controller. 
     
     
       5. The apparatus of  claim 4 , further comprising a decoder to decode transactions intended for the second interrupt controller. 
     
     
       6. The apparatus of  claim 5 , further comprising redirection logic to redirect transactions intended for the second interrupt controller to the random access memory. 
     
     
       7. The apparatus of  claim 1 , further comprising messaging logic to construct an interrupt message for each of the plurality of interrupts handled by the emulation logic. 
     
     
       8. A method comprising:
 receiving an interrupt request; 
 blocking the interrupt request in a first interrupt controller having a first programming model; and 
 emulating a second interrupt controller to handle the interrupt request, the second interrupt controller having a second programming model different from the first programming model, wherein the second programming model is an Advanced Programmable Interrupt Controller programming model. 
 
     
     
       9. The method of  claim 8 , further comprising determining whether the interrupt request is to be handled locally, wherein blocking the interrupt request and emulating the second interrupt controller is performed only if the interrupt request is not to be handled locally. 
     
     
       10. The method of  claim 9 , wherein the second interrupt controller is an input/output Advanced Programmable Interrupt Controller. 
     
     
       11. The method of  claim 10 , further comprising finding, in a random access memory, a redirection table entry corresponding to the interrupt request. 
     
     
       12. The method of  claim 11 , further comprising constructing, based on information from the redirection table entry, an interrupt message. 
     
     
       13. The method of  claim 12 , further comprising sending the interrupt message to a local Advanced Programmable Interrupt Controller. 
     
     
       14. The method of  claim 13 , further comprising receiving an end-of-interrupt message from the local Advanced Programmable interrupt Controller. 
     
     
       15. The method of  claim 14 , further comprising finding, in the random access memory, the redirection table entry based on vector information from the end-of-interrupt message. 
     
     
       16. The method of  claim 15 , further comprising unblocking the interrupt request in the first interrupt controller in response to finding the redirection table entry based on vector information from the end-of-interrupt message. 
     
     
       17. The method of  claim 11 , further comprising, prior to finding the redirection table entry in the random access memory, storing information in a location allocated for the redirection table entry in the random access memory, the information received in a transaction intended for the input/output Advanced Programmable Interrupt Controller. 
     
     
       18. The method of  claim 17 , further comprising, prior to storing information in a location allocated for the redirection table entry in the random access memory, decoding the transaction intended for the input/output Advanced Programmable Interrupt Controller and redirecting the transaction to the random access memory. 
     
     
       19. A system comprising:
 a first processor including a first interrupt controller having a first programming model, wherein the first programming model is an Advanced Programmable Interrupt Controller programming model; 
 a second processor to control a plurality of input/output devices, the second processor including a second interrupt controller having a programming model different from the first programming model; and 
 firmware to cause the second processor to emulate the first interrupt controller and to block interrupt requests to the second interrupt controller in response to an interrupt request that is not to be serviced by the second processor. 
 
     
     
       20. The system of  claim 19 , further comprising:
 a random access memory; and 
 redirection logic to decode transactions intended for the first interrupt controller and 
 redirect the transactions to the random access memory.