P
US8975681B2ActiveUtilityPatentIndex 63

Semiconductor device

Assignee: MITSUBISHI ELECTRIC CORPPriority: Sep 19, 2012Filed: May 31, 2013Granted: Mar 10, 2015
Est. expirySep 19, 2032(~6.2 yrs left)· nominal 20-yr term from priority
Inventors:AKIYAMA HAJIMEOKADA AKIRA
H10D 84/813H10D 62/393H10D 84/141H10D 64/117H10D 64/112H10D 62/116H10D 62/115H10D 62/112H10D 62/109H10D 62/107H10D 62/106H10D 62/105H10D 30/668H10D 30/665H10D 12/481H10D 84/811H01L 27/0629
63
PatentIndex Score
2
Cited by
3
References
8
Claims

Abstract

In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to each other; 
 an element-formed region formed in a predetermined region in said first main surface of said semiconductor substrate and having a predetermined semiconductor element disposed to conduct current between said first main surface and said second main surface; 
 an electric-field reduction region formed in said first main surface of said semiconductor substrate and located laterally with respect to said element-formed region so that said electric-field reduction region contacts said element-formed region; and 
 an insulating protective film formed to cover said first main surface and having a predetermined dielectric constant, 
 said electric-field reduction region including:
 an insulating region formed from said first main surface to a predetermined depth and having a lower dielectric constant than said dielectric constant of said protective film; 
 a channel stopper region of the first conductivity type formed opposite to said element-formed region with respect to said insulating region and spaced from said insulating region; 
 a plurality of floating electrodes arranged so that said electrodes have coupling capacitor components along a direction connecting said element-formed region and said channel stopper region; and 
 a second-conductivity-type region formed to extend deeper from said insulating region. 
 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein said insulating region is a porous-oxide-film region. 
     
     
       3. The semiconductor device according to  claim 1 , wherein
 said plurality of floating electrodes include:
 a first floating electrode disposed relatively lower; and 
 a second floating electrode disposed relatively higher, and 
 
 said first floating electrode and said second floating electrode are disposed so that capacitive coupling between said first floating electrode and said second floating electrode has coupling capacitor components along said direction. 
 
     
     
       4. The semiconductor device according to  claim 1 , further comprising a plurality of trenches spaced from each other along said direction and formed through said insulating region to reach said second-conductivity-type region, wherein
 said plurality of floating electrodes are formed to respectively cover respective inner walls of said plurality of trenches. 
 
     
     
       5. The semiconductor device according to  claim 3 , further comprising a plurality of trenches spaced from each other along said direction and formed through said insulating region to reach said second-conductivity-type region, wherein
 said first floating electrode is formed on a part of each of respective inner walls of said plurality of trenches, and 
 said second floating electrode is formed on a part of said insulating region that is located at an opening end of said trench. 
 
     
     
       6. The semiconductor device according to  claim 1 , wherein said insulating region is formed so that said insulating region located on a side of said channel stopper region is deeper than said insulating region located on a side of said element-formed region. 
     
     
       7. The semiconductor device according to  claim 1 , wherein said second-conductivity-type region is guard ring regions formed to be spaced from each other along said direction. 
     
     
       8. The semiconductor device according to  claim 1 , wherein said second-conductivity-type region is a RESURF region formed to surround lateral and lower sides of said insulating region.

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