Nonvolatile memory device and method for fabricating the same

Abstract

A nonvolatile memory device includes a unit cell with a transistor and a capacitor. The transistor is disposed on a substrate having a tunneling region and a channel region and includes a floating gate crossing both the tunneling region and the channel region. The capacitor is coupled to the floating gate.

What is claimed is: 
     
       1. A unit cell of a nonvolatile memory device, comprising:
 a transistor and a capacitor, 
 wherein the transistor comprises: 
 a tunneling region disposed in a substrate; 
 a channel region contacting with the tunneling region; 
 a drain region disposed in the tunneling region; 
 a source region disposed in the channel region; 
 a floating gate crossing both the tunneling region and the channel region; 
 a spacer disposed on both sidewalls of the floating gate; and 
 a first gate dielectric layer having a first thickness disposed between the tunneling region and the floating gate; 
 a second gate dielectric layer having a second thickness greater than the first thickness disposed between the channel region and the floating gate; and 
 wherein the capacitor is coupled to the floating gate through a contact plug, 
 wherein each the drain region and the source region comprises a lightly doped region and a highly doped region, and 
 the lightly doped region has shallower depth than the highly doped region, and 
 the lightly doped region and the highly doped region are partially overlapped with the spacer, and 
 the drain region is symmetrical with respect to the source region, 
 wherein a change in the thickness between the first gate dielectric layer to the second gate dielectric layer starts from a boundary between the tunneling region and the channel region. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , wherein the tunneling region and the channel region comprise impurity regions formed in the substrate and having complementary conductivity types. 
     
     
       3. The nonvolatile memory device of  claim 1 , wherein the tunneling region comprises a first impurity region of a second conductivity type, and the channel region comprises a second impurity region of a first conductivity type. 
     
     
       4. The nonvolatile memory device of  claim 3 , wherein the first impurity region and the second impurity region comprise logic wells. 
     
     
       5. The nonvolatile memory device of  claim 3 , wherein the first impurity region and the second impurity region are in contact with each other under the floating gate. 
     
     
       6. The nonvolatile memory device of  claim 3 , wherein the first impurity region and the second impurity region are spaced apart from each other by a predetermined interval under the floating gate. 
     
     
       7. The nonvolatile memory device of  claim 3 , wherein the first impurity region and the second impurity region are partially overlapped with each other under the floating gate. 
     
     
       8. The nonvolatile memory device of  claim 7 , further comprising an isolation layer disposed in the first impurity region and overlapped with one end of the floating gate. 
     
     
       9. The nonvolatile memory device of  claim 1 , wherein the capacitor has any one shape selected from the group consisting of a flat plate shape, a concave shape, a convex shape, a cylindrical shape, and a pillar shape. 
     
     
       10. The nonvolatile memory device of  claim 1 , wherein the unit cell further comprises a junction region in the substrate on one side of the floating gate, on the other side of the floating gate, or on both sides of the floating gate. 
     
     
       11. The nonvolatile memory device of  claim 1 , further comprising a driving unit configured to control a driving of the unit cell. 
     
     
       12. The nonvolatile memory device of  claim 11 , wherein the driving unit comprises an NMOS transistor, a PMOS transistor, or a CMOS transistor in which the NMOS transistor and the PMOS transistor are coupled. 
     
     
       13. The nonvolatile memory device of  claim 12 , wherein the NMOS transistor comprises:
 an N-type impurity region and a P-type impurity region disposed in the substrate; 
 a gate electrode disposed on the substrate and crossing both the N-type impurity region and the P-type impurity region; 
 a gate dielectric layer disposed between the substrate and the gate electrode; 
 an N-type drain region disposed in the N-type impurity region on one side of the gate electrode; and 
 an N-type source region disposed in the P-type impurity region on the other side of the gate electrode. 
 
     
     
       14. The nonvolatile memory device of  claim 13 , further comprising an isolation layer disposed in the N-type impurity region, overlapped with one end of the gate electrode, and spacing the N-type drain region from the gate electrode by a predetermined interval. 
     
     
       15. The nonvolatile memory device of  claim 13 , wherein the substrate comprises a P-type substrate, the N-type impurity region comprises a logic well, and the P-type impurity region comprises the P-type substrate. 
     
     
       16. The nonvolatile memory device of  claim 12 , wherein the PMOS transistor comprises:
 a P-type impurity region and an N-type impurity region disposed in the substrate; 
 a gate electrode disposed on the substrate and crossing both the P-type impurity region and the N-type impurity region; 
 a gate dielectric layer disposed between the substrate and the gate electrode; 
 a P-type drain region disposed in the P-type impurity region on one side of the gate electrode; and 
 a P-type source region disposed in the N-type impurity region on the other side of the gate electrode. 
 
     
     
       17. The nonvolatile memory device of  claim 16 , further comprising an isolation layer disposed in the P-type impurity region, overlapped with one end of the gate electrode, and spacing the P-type drain region from the gate electrode by a predetermined interval. 
     
     
       18. The nonvolatile memory device of  claim 16 , wherein the substrate comprises an N-type substrate, the P-type impurity region comprises a logic well, and the N-type impurity region comprises the N-type substrate. 
     
     
       19. The nonvolatile memory device of  claim 17 , wherein the P-type impurity region and the N-type impurity region comprise logic wells. 
     
     
       20. The nonvolatile memory device of  claim 19 , wherein the P-type impurity region and the N-type impurity region are in contact with each other under the gate electrode. 
     
     
       21. The nonvolatile memory device of  claim 19 , wherein the P-type impurity region and the N-type impurity region are spaced apart from each other by a predetermined interval under the gate electrode. 
     
     
       22. The nonvolatile memory device of  claim 19 , wherein the P-type impurity region and the N-type impurity region are partially overlapped with each other under the gate electrode. 
     
     
       23. The nonvolatile memory device of  claim 1 , wherein only the first gate dielectric is disposed in the tunneling region and only the second gate dielectric is disposed on the channel region. 
     
     
       24. A nonvolatile memory device, comprising:
 a first well having a second conductivity type disposed in a substrate; 
 a second well having a first conductivity type and contacted with the first well; 
 a floating gate disposed on the substrate and crossing both the first well and the second well; 
 a gate dielectric layer disposed between the substrate and the floating gate; 
 a first isolation layer disposed in the first well overlapped with the floating gate; 
 a drain region having the second conductivity disposed in the first well and spaced apart from the floating gate by the first isolation layer; 
 a source region having the second conductivity type disposed in the second well on the other side of the floating gate; 
 a capacitor having a structure in which a bottom electrode, a dielectric layer, and a top electrode are sequentially stacked, and the bottom electrode is coupled to the floating gate; and 
 a spacer disposed on sidewalls of the floating gate; 
 wherein the first isolation layer is in contact with the drain region, 
 wherein the source region comprises a lightly doped region and a highly doped region, and the lightly doped region has a shallower depth than the highly doped region, and 
 the drain region and the first isolation layer are partially overlapped with the spacer, wherein the spacer is in contact with a boundary between the first isolation layer and the drain region. 
 
     
     
       25. The nonvolatile memory device of  claim 24 , wherein the first well and the second well are in contact with each other under the floating gate. 
     
     
       26. The nonvolatile memory device of  claim 24 , wherein the first well and the second well are spaced apart from each other by a predetermined interval under the floating gate. 
     
     
       27. The nonvolatile memory device of  claim 24 , wherein the first well and the second well are partially overlapped with each other under the floating gate. 
     
     
       28. The nonvolatile memory device of  claim 27 , wherein the first isolation layer is overlapped with the floating gate. 
     
     
       29. The nonvolatile memory device of  claim 24 , wherein the gate dielectric layer comprises a first gate dielectric layer on the first well and a second gate dielectric layer on the second well, and the thickness of the first gate dielectric layer is substantially equal to the thickness of the second gate dielectric layer. 
     
     
       30. The nonvolatile memory device of  claim 24 , wherein the gate dielectric layer comprises a first gate dielectric layer on the first well and a second gate dielectric layer on the second well, and the thickness of the second gate dielectric layer is larger than the thickness of the first gate dielectric layer. 
     
     
       31. The nonvolatile memory device of  claim 24 , wherein the capacitor has any one shape selected from the group consisting of a flat plate shape, a concave shape, a convex shape, a cylindrical shape, and a pillar shape. 
     
     
       32. The nonvolatile memory device of  claim 24 , further comprising:
 a word line coupled to the top electrode of the capacitor; 
 a bit line coupled to the drain region; and 
 a source line coupled to the source region. 
 
     
     
       33. The nonvolatile memory device of  claim 32 , wherein, upon a program operation, a program voltage is applied to the word line and a ground voltage is applied to the bit line. 
     
     
       34. The nonvolatile memory device of  claim 32 , wherein, upon an erase operation, an erase voltage is applied to the bit line and a ground voltage is applied to the word line. 
     
     
       35. The nonvolatile memory device of  claim 34 , wherein the source line is floated. 
     
     
       36. The nonvolatile memory device of  claim 32 , wherein, upon a read operation, a read voltage is applied to the word line, a voltage higher or lower than a ground voltage is applied to the bit line, and the ground voltage is applied to the source line. 
     
     
       37. The nonvolatile memory device of  claim 24 , wherein the spacer reaches to a portion of the drain region starting from a portion of the isolation layer. 
     
     
       38. The nonvolatile memory device of  claim 24 , further comprising a second isolation layer in contact with the drain region. 
     
     
       39. The nonvolatile memory device of  claim 38 , wherein the spacer is in contact with the drain region between the first isolation layer and the second isolation layer.