Sense amplifier

Abstract

A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.

What is claimed is: 
     
       1. A sense amplifier comprising:
 a cross coupled pair of inverters having a first inverter output, a second inverter output, a first end, a second end, and a third end; 
 a pre-charge and equalizing circuit electrically coupled between the first inverter output and the second inverter output; 
 a first data line; 
 a second data line; 
 a first switch between the first data line and the first inverter output; 
 a second switch between the second data line and the second inverter output; 
 a first transistor; 
 a second transistor; 
 a capacitive device; 
 a NAND gate; and 
 an inverter, 
 wherein
 the first end is configured to receive a first supply voltage; 
 the second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor; 
 the third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor; 
 a second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal; 
 a third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage; 
 a first input of the NAND gate is configured to receive a second control signal; 
 a second input of the NAND gate is configured to receive a third control signal usable to control the first switch and the second switch; and 
 the inverter is configured to receive the second control signal and generate the first control signal usable to control the first transistor and the second transistor. 
 
 
     
     
       2. The sense amplifier of  claim 1 , wherein
 the cross coupled pair of inverters includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; 
 a third NMOS transistor is configured to serve as the first transistor; 
 a fourth NMOS transistor is configured to serve as the second transistor; 
 a source of the first PMOS transistor is coupled with a source of the second PMOS transistor, and serves as the first end; 
 a drain of the first PMOS transistor is coupled with the first inverter output, a drain of the first NMOS transistor, a gate of the second PMOS transistor, and a gate of the second NMOS transistor; 
 a drain of the second PMOS transistor is coupled with the second inverter output, a drain of the second NMOS transistor, a gate of the first PMOS transistor, and a gate of the first NMOS transistor; 
 a source of the first NMOS transistor is coupled with a drain of the third NMOS transistor, and serves as the second end; 
 a source of the second NMOS transistor is coupled with a drain of the fourth NMOS transistor, and serve as the third end; 
 a source of the third NMOS transistor serves as the third terminal of the first transistor; and 
 a source of the fourth NMOS transistor serves as the third terminal of the second transistor. 
 
     
     
       3. The sense amplifier of  claim 2 , wherein
 the pre-charge and equalizing circuit comprises a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor; and 
 a memory cell electrically coupled with the first data line and the second data line. 
 
     
     
       4. A sense amplifier comprising:
 a cross coupled pair of inverters having a first inverter output, a second inverter output, a first end, a second end, and a third end; 
 a pre-charge and equalizing circuit electrically coupled between the first inverter output and the second inverter output; 
 a first data line; 
 a second data line; 
 a first switch between the first data line and the first inverter output; 
 a second switch between the second data line and the second inverter output; 
 a first transistor; 
 a second transistor; 
 a capacitive device; and 
 an AND gate, 
 wherein
 the first end is configured to receive a first supply voltage; 
 the second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor; 
 the third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor; 
 a second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal; 
 a third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage; 
 a first input of the AND gate is configured to receive the first control signal usable to control the first transistor and the second transistor; and 
 a second input of the AND gate is configured to receive a second control signal usable to control the first switch and the second switch. 
 
 
     
     
       5. The sense amplifier of  claim 4 , wherein
 the cross coupled pair of inverters includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; 
 a third PMOS transistor is configured to serve as the first transistor; 
 a fourth PMOS transistor is configured to serve as the second transistor; 
 a source of the first NMOS transistor is coupled with a source of the second NMOS transistor, and serves as the first end; 
 a drain of the first NMOS transistor is coupled with the first inverter output, a drain of the first PMOS transistor, a gate of the second NMOS transistor, and a gate of the second PMOS transistor; 
 a drain of the second NMOS transistor is coupled with the second inverter output, a drain of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the first PMOS transistor; 
 a source of the first PMOS transistor is coupled with a drain of the third PMOS transistor, and serves as the second end; 
 a source of the second PMOS transistor is coupled with a drain of the fourth PMOS transistor, and serve as the third end; 
 a source of the third PMOS transistor serves as the third terminal of the first transistor; and 
 a source of the fourth PMOS transistor serves as the third terminal of the second transistor. 
 
     
     
       6. The sense amplifier of  claim 5 , wherein
 the pre-charge and equalizing circuit comprises a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; and 
 a memory cell electrically coupled with the first data line and the second data line. 
 
     
     
       7. A method comprising:
 generating a first control signal by using an AND gate or a NAND gate based on a second control signal and a third control signal; 
 applying a voltage value to a first data line and a second data line based on the first control signal; and 
 enabling a sense amplifier based on the second control signal, 
 wherein the method further comprises, during a time period the sense amplifier is enabled:
 causing a first node of the sense amplifier to have a first voltage value towards a voltage value at the first data line and a second node of the sense amplifier to have a second voltage value towards a voltage value at the second data line; 
 causing a differential voltage between the first data line and the second data line to develop based on the third control signal; and 
 sensing the developed differential voltage between the first data line and the second data line. 
 
 
     
     
       8. The method of  claim 7 , wherein
 the first voltage value towards the voltage value at the first data line is based on a threshold voltage of a first transistor of the sense amplifier; and 
 the second voltage value towards the voltage value at the second data line is based on a threshold voltage of a second transistor of the sense amplifier. 
 
     
     
       9. The method of  claim 7 , further comprising:
 electrically coupling a first node of a memory cell to a third data line and a second node of the memory cell to a fourth data line based on the third control signal. 
 
     
     
       10. The method of  claim 9 , wherein
 electrically coupling a first node of a memory cell to the third data line and a second node of the memory cell to the fourth data line comprises:
 activating a control line of the memory cell that is coupled with the third data line and the fourth data line; and 
 electrically coupling the third data line with the first data line and the fourth data line with the second data line. 
 
 
     
     
       11. The method of  claim 7 , wherein
 the sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; 
 a source of the first PMOS transistor is coupled with a source of the second PMOS transistor, and serves as a first end of a cross coupled pair of inverters of the sense amplifier; 
 a drain of the first PMOS transistor is coupled with a drain of the first NMOS transistor, a gate of the second PMOS transistor, and a gate of the second NMOS transistor; 
 a drain of the second PMOS transistor is coupled with a drain of the second NMOS transistor, a gate of the first PMOS transistor, and a gate of the first NMOS transistor; 
 a source of the first NMOS transistor is coupled with a drain of the third NMOS transistor, and serves as a second end of the cross coupled pair of inverters, the second end coupled with the first node; 
 a source of the second NMOS transistor is coupled with a drain of the fourth NMOS transistor, and serve as a third end of the cross coupled pair of inverters, the third end coupled with the second node; and 
 a source of the third NMOS transistor is coupled with a source of the fourth NMOS transistor, and is configured to receive a voltage. 
 
     
     
       12. The method of  claim 7 , wherein
 the sense amplifier includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; 
 a source of the first NMOS transistor is coupled with a source of the second NMOS transistor, and serves as a first end of a cross coupled pair of inverters of the sense amplifier; 
 a drain of the first NMOS transistor is coupled with a drain of the first PMOS transistor, a gate of the second NMOS transistor, and a gate of the second PMOS transistor; 
 a drain of the second NMOS transistor is coupled with a drain of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the first PMOS transistor; 
 a source of the first PMOS transistor is coupled with a drain of the third PMOS transistor, and serves as a second end of the cross coupled pair of inverters, the second end coupled with the first node; 
 a source of the second PMOS transistor is coupled with a drain of the fourth PMOS transistor, and serve as a third end of the cross coupled pair of inverters, the third end coupled with the second node; and 
 a source of the third PMOS transistor is coupled with a source of the fourth PMOS transistor, and is configured to receive a voltage. 
 
     
     
       13. A method comprising:
 generating a first control signal by using an AND gate or a NAND gate based on a second control signal and a third control signal; 
 electrically coupling a first node of a memory cell with a first data line and a second node of the memory cell with a second data line; 
 electrically coupling the first data line with a third data line and the second data line with a fourth data line based on the third control signal; 
 applying a voltage value to the third data line and the fourth data line based on the first control signal; and 
 enabling a sense amplifier based on the second control signal, 
 wherein the method further comprises, during a time period the sense amplifier is enabled:
 causing a first node of the sense amplifier to have a first voltage value closer a voltage value at the third data line based on a threshold voltage of a first transistor of the sense amplifier; 
 causing a second node of the sense amplifier to have a second voltage value closer to a voltage value at the fourth data line based on a threshold voltage of a second transistor of the sense amplifier; 
 causing a differential voltage between the third data line and the fourth data line to develop based on the third control signal; and 
 sensing the developed differential voltage between the first data line and the second data line. 
 
 
     
     
       14. The method of  claim 13 , wherein
 electrically coupling a first node of a memory cell with a first data line and a second node of the memory cell with a second data line comprises activating a control line coupled with the memory cell. 
 
     
     
       15. The method of  claim 13 , wherein
 electrically coupling the first data line with a third data line is through a third transistor; and 
 electrically coupling the second data line with a fourth data line is through a fourth transistor. 
 
     
     
       16. The method of  claim 13 , wherein
 applying a voltage value to the third data line and the fourth data line includes controlling a third transistor, a fourth transistor and a fifth transistor that are coupled with the third data line and the fourth data line. 
 
     
     
       17. The method of  claim 13 , wherein
 the first transistor, the second transistor, a third transistor and a fourth transistor form a cross coupled pair of inverters of the sense amplifier. 
 
     
     
       18. The method of  claim 13 , wherein
 the sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; 
 a source of the first PMOS transistor is coupled with a source of the second PMOS transistor, and serves as a first end of a cross coupled pair of inverters of the sense amplifier; 
 a drain of the first PMOS transistor is coupled with a drain of the first NMOS transistor, a gate of the second PMOS transistor, and a gate of the second NMOS transistor; 
 a drain of the second PMOS transistor is coupled with a drain of the second NMOS transistor, a gate of the first PMOS transistor, and a gate of the first NMOS transistor; 
 a source of the first NMOS transistor is coupled with a drain of the third NMOS transistor, and serves as a second end of the cross coupled pair of inverters, the second end coupled with the first node; 
 a source of the second NMOS transistor is coupled with a drain of the fourth NMOS transistor, and serve as a third end of the cross coupled pair of inverters, the third end coupled with the second node; and 
 a source of the third NMOS transistor is coupled with a source of the fourth NMOS transistor, and is configured to receive a voltage. 
 
     
     
       19. The method of  claim 13 , wherein
 the sense amplifier includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; 
 a source of the first NMOS transistor is coupled with a source of the second NMOS transistor, and serves as a first end of a cross coupled pair of inverters of the sense amplifier; 
 a drain of the first NMOS transistor is coupled with a drain of the first PMOS transistor, a gate of the second NMOS transistor, and a gate of the second PMOS transistor; 
 a drain of the second NMOS transistor is coupled with a drain of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the first PMOS transistor; 
 a source of the first PMOS transistor is coupled with a drain of the third PMOS transistor and serves as a second end of the cross coupled pair of inverters, the second end coupled with the first node; 
 a source of the second PMOS transistor is coupled with a drain of the fourth PMOS transistor, and serve as a third end of the cross coupled pair of inverters, the third end coupled with the second node; and 
 a source of the third PMOS transistor is coupled with a source of the fourth PMOS transistor, and is configured to receive a voltage.