Integrated circuit, semiconductor device and method of manufacturing a semiconductor device

Abstract

An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.

What is claimed is: 
     
       1. An integrated circuit including a semiconductor device, comprising:
 a power component comprising a plurality of trenches in a cell array, the plurality of trenches running in a first direction; 
 a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component; and 
 an isolation trench running in a second direction different from the first direction, an insulating material being disposed in the isolation trench, the isolation trench being disposed between the sensor component and the power component along the first direction. 
 
     
     
       2. The integrated circuit according to  claim 1 , wherein the power component comprises a power transistor including a source region, a drain region, a body region and a gate electrode, the gate electrode being adjacent to the body region, and
 the sensor cell comprises a sensor transistor including a source region, a drain region, a body region and a gate electrode, the body region and the source region of the power transistor being laterally insulated from the body region and the source region of the sensor transistor by an isolation trench. 
 
     
     
       3. The integrated circuit according to  claim 2 , wherein the source regions of the power transistor and of the sensor transistor are disposed adjacent to a first main surface of a semiconductor substrate, and the isolation trenches are disposed adjacent to the first main surface. 
     
     
       4. The integrated circuit according to  claim 2 , wherein the gate electrode of the power transistor and the gate electrode of the sensor transistor are disposed in one of the plurality of trenches and are connected with each other to form a common gate electrode. 
     
     
       5. The integrated circuit according to  claim 2 , wherein the plurality of trenches run parallel to one another in a same direction and a region between adjacent trenches defines a mesa region, a plurality of the mesa regions running parallel to one another in the direction of the plurality of trenches, the source region and the body region of each of the power transistors and the sensor transistors being disposed in the mesa regions. 
     
     
       6. The integrated circuit according to  claim 5 , wherein the isolation trenches intersect at least one of the mesa regions. 
     
     
       7. The integrated circuit according to  claim 6 , wherein the isolation trenches extend to a depth beneath a lower side of the body regions. 
     
     
       8. The integrated circuit according to  claim 2 , wherein two isolation trenches are adjacent to one source portion of the sensor transistor. 
     
     
       9. The integrated circuit according to  claim 8 , wherein a width of the sensor transistor is configured to be adjusted by setting a distance between adjacent isolation trenches. 
     
     
       10. The integrated circuit according to  claim 2 , wherein the drain region of the power transistor and the drain region of the sensor transistor are connected to a drain potential, and the gate electrode of the power transistor and the gate electrode of the sensor transistor are connected to a gate potential. 
     
     
       11. The integrated circuit according to  claim 4 , further comprising a conductive material disposed in the isolation trenches and connected with the common gate electrode. 
     
     
       12. The integrated circuit according to  claim 1 , wherein the integrated circuit is configured to operate as a power switch. 
     
     
       13. The integrated circuit according to  claim 1 , further comprising a doped region disposed between the isolation trench and the power component. 
     
     
       14. The integrated circuit according to  claim 13 , further comprising an additional isolation trench disposed between the doped region and the power component. 
     
     
       15. A semiconductor device including a transistor array, comprising a plurality of first transistors and at least a second transistor, at least one first and one second transistor being disposed adjacent to each other, each of the first and second transistors comprising:
 a source region disposed adjacent to a first main surface of a semiconductor substrate; and 
 a gate electrode disposed in a trench formed in the first main surface, the gate electrode of the first transistor and the gate electrode of the second transistor being connected to a common gate potential; 
 the semiconductor device further comprising an isolation trench disposed between the source region of the first transistor and the source region of the second transistor along the first direction, the source region of the first transistor being connected to a first source potential, the source region of the second transistor being connected to a second source potential, the first source potential being different from the second source potential. 
 
     
     
       16. The semiconductor device according to  claim 15 , wherein each of the first and second transistors further comprises a drain region adjacent to a second main surface of the semiconductor substrate, the second main surface being opposed to the first main surface, the drain region of the first transistor and the drain region of the second transistor being connected to a common drain potential. 
     
     
       17. The semiconductor device according to  claim 15 , wherein the source region is disposed in a mesa defined by parallel gate trenches, wherein the first and the second transistors further comprise a body region disposed in the mesa beneath each of the source regions and a conductive material disposed in the gate trenches forming the gate electrode of the first and second transistors. 
     
     
       18. The semiconductor device according to  claim 15 , wherein the semiconductor device is configured to operate as a power switch. 
     
     
       19. The semiconductor device according to  claim 15 , wherein the first transistor is operable as a power transistor and the second transistor is operable as a sensor transistor. 
     
     
       20. The semiconductor device according to  claim 15 , further comprising a doped region disposed between the isolation trench and the first transistor. 
     
     
       21. The semiconductor device according to  claim 15 , further comprising an additional isolation trench disposed between the doped region and the first transistor.