Semiconductor device and method of fabricating the same

Abstract

Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first semiconductor layer having a first region with a first device and a second region with a second device; 
 a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; 
 a drain provided on a lower surface of the first region of the first semiconductor layer; and 
 a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer. 
 
     
     
       2. The semiconductor device of  claim 1 , further comprising a sidewall insulation pattern between the drain and the second semiconductor layer. 
     
     
       3. The semiconductor device of  claim 1 , further comprising an ohmic contact layer between the first semiconductor layer and the drain. 
     
     
       4. The semiconductor device of  claim 1 , wherein the drain extends on a lower surface of the second semiconductor layer. 
     
     
       5. The semiconductor device of  claim 1 , wherein the device isolation pattern penetrates the first semiconductor layer and extends into the second semiconductor layer. 
     
     
       6. The semiconductor device of  claim 1 , wherein a conductive type of the first semiconductor layer is an n-type, and a conductive type of the second semiconductor layer is a p-type. 
     
     
       7. The semiconductor device of  claim 6 , wherein the first semiconductor layer comprises a first epi layer contacting the second semiconductor layer and a second epi layer on the first epi layer; and the first epi layer has an impurity concentration higher than that of the second epi layer. 
     
     
       8. The semiconductor device of  claim 1 , wherein the first device is a diffused metal-oxide-semiconductor (DMOS) transistor. 
     
     
       9. The semiconductor device of  claim 1 , wherein the first device comprises a source and a buried gate electrode, wherein the source and the buried gate electrode are connected to metal lines provided on the first semiconductor layer. 
     
     
       10. The semiconductor device of  claim 1 , wherein the second device is a complementary metal-oxide semiconductor (CMOS) device. 
     
     
       11. The semiconductor device of  claim 1 , wherein the first semiconductor layer further has a third region with a third device, wherein the third device is a bipolar transistor. 
     
     
       12. A method of fabricating a semiconductor device, the method comprising:
 sequentially forming first and second epi layers on a substrate having a first region, a second region, and a third region; 
 removing a portion of the first region of the substrate to expose the first epi layer; and 
 forming a drain on a lower surface of the exposed first epi layer. 
 
     
     
       13. The method of  claim 12 , wherein the forming of the drain comprises performing a plating process or a screen print process. 
     
     
       14. The method of  claim 12 , further comprising forming device isolation patterns on the substrate,
 wherein the forming of the device isolation patterns comprises: 
 forming trenches penetrating the first and second epi layers on the substrate and extending into the substrate; 
 forming trench insulation patterns covering a sidewall of the trenches; and 
 forming trench gap fill patterns filling the trenches where the trench insulation patterns are formed, 
 wherein the trench gap fill patterns comprise a polycrystalline silicon layer. 
 
     
     
       15. The method of  claim 12 , further comprising thinning the substrate before the removing of the portion of the first region, wherein the thinning of the substrate comprises performing a grinding process. 
     
     
       16. The method of  claim 12 , further comprising forming a sidewall insulation pattern on a sidewall of the substrate where the portion of the first region is removed before the forming of the drain,
 wherein the forming of the sidewall insulation pattern comprises: 
 forming a protective oxide layer covering the sidewall on the lower surface of the substrate region; and 
 performing a blanket anisotropic etching process on the lower surface of the substrate where the protective layer is formed. 
 
     
     
       17. The method of  claim 12 , further comprising forming an ohmic contact layer on a lower surface of the exposed first epi layer before the forming of the drain, wherein the forming of the ohmic contact layer comprises performing a metal deposition process or a plating process. 
     
     
       18. The method of  claim 12 , further comprising:
 forming a DMOS device on the first region; 
 forming a CMOS device on the second region; and 
 forming a bipolar device on the third region.