P
US9129839B2ActiveUtilityPatentIndex 63

Method of fabricating a FinFET device

Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Mar 12, 2013Filed: Sep 4, 2014Granted: Sep 8, 2015
Est. expiryMar 12, 2033(~6.7 yrs left)· nominal 20-yr term from priority
Inventors:SHIEH MING-FENGCHEN CHEN-YU
H10P 50/695H10D 64/01326H10W 10/01H10W 10/00H10D 84/0158H10D 84/038H10D 62/115H10D 62/10H10D 30/0243H10D 84/834H01L 21/823431H01L 29/0649H01L 27/0886H01L 29/6681H01L 21/76H01L 29/06H01L 21/3086H01L 21/28123
63
PatentIndex Score
3
Cited by
10
References
20
Claims

Abstract

A semiconductor device includes a substrate and a plurality of fin structures. A first fin structure and a second fin structure are spaced at a distance D 1 . A first dummy fin structure is adjacent to the first fin structure, and a second dummy fin structure is adjacent to the second fin structure. The device further includes an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures. The fin structures are arranged such that a distance D 2 between the first fin structure and the first dummy fin structure is greater than the distance D 1.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate; 
 a first fin structure and a second fin structure spaced at a distance D 1 ; 
 a first dummy fin structure adjacent to the first fin structure without any intervening fin structure, and a second dummy fin structure adjacent to the second fin structure without any intervening fin structure; and 
 an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures; 
 wherein a distance D 2  between the first fin structure and the first dummy fin structure is greater than the distance D 1 . 
 
     
     
       2. The device of  claim 1 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon. 
     
     
       3. A semiconductor device, comprising:
 a substrate; 
 a first fin structure and a second fin structure spaced at a distance D 1 ; 
 a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and 
 an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures; 
 wherein a distance D 2  between the first fin structure and the first dummy fin structure is greater than the distance D 1 , and 
 wherein the first and second fin structures include amorphous carbon and silicon oxynitride. 
 
     
     
       4. A semiconductor device, comprising:
 a substrate; 
 a first fin structure and a second fin structure spaced; 
 a first dummy fin structure adjacent to the first fin structure without any intervening fin structure, and a second dummy fin structure adjacent to the second fin structure without any intervening fin structure; and 
 an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures; 
 wherein the first and second fin structures are spaced at a distance D 1 , the first fin structure and the first dummy fin structure are spaced at a distance D 2 , and D 2  is greater than two times of D 1 . 
 
     
     
       5. The device of  claim 4 , wherein the isolation structure buries the dummy fins. 
     
     
       6. The device of  claim 4 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon. 
     
     
       7. The device of  claim 4 , wherein the substrate includes layers of silicon, amorphous carbon (APF), and silicon oxynitride. 
     
     
       8. A semiconductor device, comprising:
 a substrate; 
 a first fin structure and a second fin structure spaced; 
 a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and 
 an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures; 
 wherein the first and second fin structures have been modified by a cut process, and 
 wherein the fin structures include layers of silicon, amorphous carbon (APF), and a capping layer. 
 
     
     
       9. The device of  claim 8 , wherein the capping layer is silicon oxynitride. 
     
     
       10. A semiconductor device, comprising:
 a substrate; 
 a first fin structure and a second fin structure; 
 a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and 
 an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures; 
 wherein the first and second fin structures include amorphous carbon and silicon oxynitride. 
 
     
     
       11. The device of  claim 10 , wherein a distance between the first fin structure and the first dummy fin structure is greater than a distance between the first fin structure and the second fin structure. 
     
     
       12. The device of  claim 10 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon. 
     
     
       13. The device of  claim 10 , wherein the first and second fin structures have been modified by a cut process. 
     
     
       14. The device of  claim 10 , wherein the substrate includes a plurality of layers. 
     
     
       15. The device of  claim 14 , wherein the plurality of layers include silicon oxide, silicon nitride, silicon oxynitride layer, or combination thereof. 
     
     
       16. The device of  claim 11 , wherein the isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. 
     
     
       17. The device of  claim 16 , wherein the isolation structure is formed using a deposition process. 
     
     
       18. The device of  claim 17 , wherein the isolation structure has a planarized surface. 
     
     
       19. The device of  claim 11 , wherein the first and second dummy fin structures have been modified by a cut process. 
     
     
       20. The device of  claim 11 , wherein the substrate includes silicon germanium.

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References (0)

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