NAND type nonvolatile semiconductor memory device and method for manufacturing same

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes: first semiconductor regions extending in a first direction and arranged in a direction crossing the first direction; control gate electrodes provided on an upper side of the first semiconductor regions, extending in a second direction different from the first direction, and arranged in a direction crossing the second direction; a charge storage layer provided in a position each of the first semiconductor regions and each of the control gate electrodes cross; a first insulating film provided between the charge storage layer and each of the first semiconductor regions; a second insulating film provided between the charge storage layer and each of the control gate electrodes; and a silicon-containing layer in contact with part of a side wall of each of the control gate electrodes and having a gradient in a silicon concentration in a direction crossing the second direction.

What is claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising:
 a plurality of first semiconductor regions extending in a first direction, and the plurality of first semiconductor regions being arranged in a direction crossing the first direction; 
 a plurality of control gate electrodes provided on an upper side of the plurality of first semiconductor regions, the plurality of control gate electrodes extending in a second direction different from the first direction, and the plurality of control gate electrodes being arranged in a direction crossing the second direction; 
 a charge storage layer provided in a position, and each of the plurality of first semiconductor regions and each of the plurality of control gate electrodes cross in the position; 
 a first insulating film provided between the charge storage layer and each of the plurality of first semiconductor regions; 
 a second insulating film provided between the charge storage layer and each of the plurality of control gate electrodes; and 
 a silicon-containing layer in contact with part of a side wall of each of the plurality of control gate electrodes, and the silicon-containing layer having a gradient in a silicon concentration in a direction crossing the second direction, 
 each of the plurality of control gate electrodes including a polysilicon-containing layer and a metal-containing layer provided on the polysilicon-containing layer, and a side wall of the metal-containing layer being covered with the silicon-containing layer. 
 
     
     
       2. The device according to  claim 1 , wherein at least part of the silicon-containing layer is oxidized or nitrided. 
     
     
       3. The device according to  claim 1 , wherein in the silicon-containing layer, the silicon concentration is lower on a side of a surface of the silicon-containing layer than on a side of a junction between the part of the side wall and the silicon-containing layer. 
     
     
       4. The device according to  claim 1 , wherein the polysilicon-containing layer has:
 a first portion having a first width in a direction crossing the second direction and the first portion being in contact with the metal-containing layer; and 
 a second portion having a second width wider than the first width and the second portion provided between the first portion and the second insulating film. 
 
     
     
       5. The device according to  claim 4 , wherein at least part of the silicon-containing layer is oxidized or nitrided. 
     
     
       6. The device according to  claim 4 , wherein in the silicon-containing layer, the silicon concentration is lower on a side of a surface of the silicon-containing layer than on a side of a junction between the part of the side wall and the silicon-containing layer. 
     
     
       7. The device according to  claim 1 , wherein the metal-containing layer includes tungsten. 
     
     
       8. The device according to  claim 7 , wherein at least part of the silicon-containing layer is oxidized or nitrided. 
     
     
       9. The device according to  claim 7 , wherein in the silicon-containing layer, the silicon concentration is lower on a side of a surface of the silicon-containing layer than on a side of a junction between the part of the side wall and the silicon-containing layer.