Integrated circuit interconnect crack monitor circuit

Abstract

A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.

What is claimed is: 
     
       1. A device, comprising:
 a first I/O interconnect; 
 a second I/O interconnect; 
 a third I/O interconnect; 
 a fourth I/O interconnect and 
 an integrated circuit die comprising
 a first conductive node coupled to the first I/O interconnect; 
 a second conductive node coupled to the second I/O interconnect; 
 a third conductive node coupled to the third I/O interconnect and 
 a fourth conductive node coupled to the first input and to the fourth I/O interconnect; and 
 a detection circuit comprising
 a first output coupled to the first conductive node to provide an integrity check signal; 
 a second output coupled to the third conductive node; 
 a first input coupled to the second conductive node to receive a first return signal based on the integrity check signal; and 
 a monitor circuit coupled to the first input to determine a first integrity characteristic of a first verified communication path, that includes the second I/O interconnect and the fourth I/O interconnect, based upon the first return signal, the first integrity characteristic being indicative of the integrity of the first verified communication path. 
 
 
 
     
     
       2. The device of  claim 1 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       3. The device of  claim 2 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect. 
 
 
     
     
       4. The device of  claim 1 , further comprising:
 a fifth I/O interconnect; and 
 a sixth I/O interconnect; wherein: 
 the integrated circuit die further comprises:
 a fifth conductive node coupled to the fifth I/O interconnect; and 
 a sixth conductive node coupled to a sixth I/O interconnect; 
 
 the detection circuit further comprises:
 a second input coupled to the fifth conductive node and to the sixth conductive node, wherein the second input receives a second return signal based on the integrity check signal; 
 the monitor circuit is further coupled to the second input to determine a second integrity characteristic of a second verified communication path that includes the fifth I/O interconnect and the sixth I/O interconnect, based upon the second return signal; and 
 
 the monitor circuit is operable to provide an indication in response to a difference between the first integrity characteristic and the second integrity characteristic being in a particular relationship to a threshold value. 
 
     
     
       5. The device of  claim 1 , wherein the device is a packaged device comprising:
 the first, second, third, fourth, fifth, and sixth I/O interconnects; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a seventh conductive node coupled to the first I/O interconnect, wherein the seventh conductive node is between the first conductive node and the first I/O interconnect; 
 an eighth conductive node coupled to the second I/O interconnect, wherein the eighth conductive node is between the second conductive node and the second I/O interconnect; 
 a ninth conductive node coupled to the third I/O interconnect, wherein the ninth conductive node is between the third conductive node and the third I/O interconnect; 
 a tenth conductive node coupled to the fourth I/O interconnect, wherein the tenth conductive node is between the fourth conductive node and the fourth I/O interconnect; 
 an eleventh conductive node coupled to the fifth I/O interconnect, wherein the eleventh conductive node is between the fifth conductive node and the fifth I/O interconnect; and 
 a twelfth conductive node coupled to the sixth I/O interconnect, wherein the twelfth conductive node is between the sixth conductive node and the sixth I/O interconnect. 
 
 
     
     
       6. The device of  claim 5 , further comprising:
 a printed circuit board (PCB) to which the packaged device is attached, the PCB comprising:
 a thirteenth conductive node coupled to the first I/O interconnect, to the second I/O interconnect and to the fifth I/O interconnect, to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect and to the fifth I/O interconnect; and 
 a fourteenth conductive node coupled to the third I/O interconnect, to the fourth I/O interconnect and to the sixth I/O interconnect to communicate the integrity check signal from the third I/O interconnect to the fourth I/O interconnect and to the sixth I/O interconnect. 
 
 
     
     
       7. The device of  claim 6 , wherein:
 the fourteenth conductive node is further coupled to electrical ground. 
 
     
     
       8. The device of  claim 5 , wherein the second, fourth, fifth and sixth I/O interconnects are substantially at corners of the packaged integrated circuit device. 
     
     
       9. The device of  claim 4 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       10. The device of  claim 9 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect. 
 
 
     
     
       11. The device of  claim 5 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       12. The device of  claim 11 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect. 
 
 
     
     
       13. The device of  claim 6 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       14. The device of  claim 13 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect. 
 
 
     
     
       15. The device of  claim 7 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       16. The device of  claim 15 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect. 
 
 
     
     
       17. The device of  claim 8 , wherein the device is a packaged device comprising:
 the first I/O interconnect; 
 the second I/O interconnect; 
 an integrated circuit package substrate to which the integrated circuit die is attached, the integrated circuit package substrate comprising:
 a third conductive node coupled to the first I/O interconnect, wherein the third conductive node is between the first conductive node and the first I/O interconnect; and 
 a fourth conductive node coupled to the second I/O interconnect; wherein the fourth conductive node is between the second conductive node and the second I/O interconnect. 
 
 
     
     
       18. The device of  claim 17 , further comprising:
 a PCB comprising:
 a first communication path coupled to the second I/O interconnect and to the first I/O interconnect to communicate the integrity check signal from the first I/O interconnect to the second I/O interconnect.