Chip debug during power gating events

Abstract

A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

What is claimed is: 
     
       1. A system for chip debug, the system comprising:
 a plurality of functional blocks; 
 a debug path coupling the plurality of functional blocks in a daisy chain configuration, wherein an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration; and 
 a debug bus steering module configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles, 
 wherein the one or more debug signals associated with the first functional block passes to the end functional block through powered-down functional blocks. 
 
     
     
       2. The system of  claim 1 , further comprising:
 a logic analyzer coupled to an output of the end functional block and configured to receive the one or more debug signals; and 
 a power gating finite state machine configured to enable and disable the one or more power gating cycles of the second functional block. 
 
     
     
       3. The system of  claim 1 , wherein the plurality of functional blocks comprises one or more power gated functional blocks, one or more non-power gated functional blocks, or a combination thereof. 
     
     
       4. The system of  claim 3 , wherein each of the one or more power gated functional blocks comprises a debug wrapper configured to pass the one or more debug signals to the debug bus steering module. 
     
     
       5. The system of  claim 1 , wherein the debug bus steering module comprises a control signal to operate the debug bus steering module in a synchronous mode of operation or an asynchronous mode of operation. 
     
     
       6. The system of  claim 1 , wherein the debug bus steering module comprises a plurality of multiplexers and control signals to concatenate the one or more debug signals with another one or more debug signals to pass the one or more debug signals and the another one or more debug signals along the debug path in a serial manner. 
     
     
       7. The system of  claim 1 , wherein the one or more debug signals are associated with debug signals associated with a power gated functional block, debug signals associated with a non-power gated functional block, or a combination thereof. 
     
     
       8. The system of  claim 1 , wherein the debug bus steering module is configured to receive a sequence of a fixed signature, then the one or more debug signals, and then the fixed signature. 
     
     
       9. The system of  claim 1 , wherein each of the plurality of functional blocks comprises one or more processing units. 
     
     
       10. The system of  claim 1 , wherein the plurality of functional blocks comprises a first functional block in a first tile and a second functional block in a second tile, and wherein the first functional block is configured to execute one or more instructions in parallel or in a pipeline manner with the second functional block. 
     
     
       11. A method for chip debug, the method comprising:
 power cycling one or more functional blocks from a plurality of functional blocks, wherein the plurality of functional blocks are coupled in a daisy chain configuration along a debug path and wherein an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration; and 
 passing one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block during the power cycling of the one or more functional blocks, 
 wherein the one or more debug signals associated with the first functional block passes to the end functional block through powered-down functional blocks. 
 
     
     
       12. The method of  claim 11 , wherein the power cycling comprises enabling and disabling power from the one or more functional blocks. 
     
     
       13. The method of  claim 11 , wherein the passing comprises passing the one or more debug signals in a synchronous manner or an asynchronous manner. 
     
     
       14. The method of  claim 11 , wherein the passing comprises concatenating the one or more debug signals with another one or more debug signals to pass the one or more debug signals and the another one or more debug signals along the debug path in a serial manner. 
     
     
       15. The method of  claim 11 , wherein the passing comprises receiving a sequence of a fixed signature, then the one or more debug signals, and then the fixed signature. 
     
     
       16. A tangible computer readable medium having stored therein one or more sequences of one or more instructions for execution by one or more processors to perform a method for chip debug, the method comprising:
 power cycling one or more functional blocks from a plurality of functional blocks, wherein the plurality of functional blocks are coupled in a daisy chain configuration along a debug path and wherein an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration; and 
 passing one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block during the power cycling of the one or more functional blocks, 
 wherein the one or more debug signals associated with the first functional block passes to the end functional block through powered-down functional blocks. 
 
     
     
       17. The tangible computer readable medium of  claim 16 , wherein the power cycling comprises enabling and disabling power from the one or more functional blocks. 
     
     
       18. The tangible computer readable medium of  claim 16 , wherein the passing comprises passing the one or more debug signals in a synchronous manner or an asynchronous manner. 
     
     
       19. The tangible computer readable medium of  claim 16 , concatenating the one or more debug signals with another one or more debug signals to pass the one or more debug signals and the another one or more debug signals along the debug path in a serial manner. 
     
     
       20. The tangible computer readable medium of  claim 16 , wherein the passing comprises receiving a sequence of a fixed signature, then the one or more debug signals, and then the fixed signature.