Reference line and bit line structure for 3D memory

Abstract

A 3D NAND flash memory includes even and odd stacks of conductive strips. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars include even and odd semiconductor films on the data storage structures connected at the bottom ends so that the semiconductor films can be thin films having a U-shaped current path. An even pad connected to the even semiconductor film and an odd pad connected to the odd semiconductor film are disposed over the even and odd stacks respectively. A segment of a reference line is connected to the even pad, and an inter-level connector is connected to the odd pad. A segment of a bit line comprises an extension contacting the inter-level connector.

What is claimed is: 
     
       1. A memory device, comprising:
 first and second stacks of conductive strips having sidewalls; 
 data storage structures on the sidewalls of the first and second stacks; 
 first and second vertical channel films on the data storage structures on the sidewalls of the first and second stacks, each first vertical channel film including a first pad over the first stack on an upper end of the first vertical channel film, and each second vertical channel film including a second pad over the second stack on an upper end of the second vertical channel film, the first and second vertical channel films being connected at bottom ends; 
 a first level of patterned conductors overlying the first and second stacks, the patterned conductors in the first level comprising a segment of a reference line and an inter-level connector, the segment of the reference line connected to the first pad, the inter-level connector connected to the second pad; 
 a second level of patterned conductors over the first level, the patterned conductors in the second level comprising a segment of a bit line, the segment of the bit line including an extension contacting the inter-level connector; and 
 a multilayered insulating structure over the first level, the multilayered insulating structure comprising a first insulating film, a second insulating film and a third insulating film, the extension comprising a fin within the first and second insulating films. 
 
     
     
       2. The memory device of  claim 1 , wherein the segment of the reference line is comprised of a conductive material and the inter-level connector is comprised of the same conductive material. 
     
     
       3. The memory device of  claim 1 , wherein the inter-level connector is comprised of a plug comprised of a conductive material in a via through an interlayer dielectric connected to the second pad, and the segment of the reference line is comprised of the conductive material in a trench through the interlayer dielectric connected to the first pad. 
     
     
       4. The memory device of  claim 1 , wherein the extension has two sides aligned with the segment of the bit line. 
     
     
       5. The memory device of  claim 1 , wherein the first and third insulating films comprise the same material, and comprise different material than the second insulating film. 
     
     
       6. The memory device of  claim 1 , wherein the segment of the reference line is disposed in direct contact with the first pad. 
     
     
       7. The memory device of  claim 6 , wherein the first pad includes a semiconductor plug over the first stack and in direct contact with the segment of the reference line. 
     
     
       8. A memory device, comprising:
 first and second stacks of conductive strips having sidewalls; 
 a plurality of U-shaped films having outside surfaces contacting data storage structures on sidewalls of the first and second stacks; 
 a plurality of first pads connected to ends of the U-shaped films in the plurality over the first stack and a plurality of second pads connected to the other ends of the U-shaped films in the plurality over the second stack; 
 a first level of patterned conductors overlying the first and second stacks, the patterned conductors in the first level comprising a segment of a reference line and a plurality of inter-level connectors, the segment of the reference line connected to the first pads in the plurality, the inter-level connectors in the plurality connected to the second pads in the plurality; 
 a second level of patterned conductors over the first level, the patterned conductors in the second level comprising a segment of a bit line, the segment of the bit line including a plurality of extensions contacting the inter-level connectors in the plurality; and 
 a multilayered insulating structure over the first level, the multilayered insulating structure comprising a first insulating film, a second insulating film and a third insulating film, a respective one of the extensions in the plurality comprising a fin within the first and second insulating films. 
 
     
     
       9. The memory device of  claim 8 , wherein a respective one of the extensions in the plurality has two sides aligned with the segment of the bit line. 
     
     
       10. The memory device of  claim 9 , wherein the second and third insulating films are made of different materials. 
     
     
       11. The memory device of  claim 8 , wherein the segment of the reference line is disposed in direct contact with the first pads in the plurality. 
     
     
       12. The memory device of  claim 8 , wherein respective one of the first pads in the plurality includes a semiconductor plug over the first stack and in direct contact with the segment of the reference line. 
     
     
       13. A method of manufacturing a memory device, comprising:
 forming first and second stacks of conductive strips having sidewalls; 
 forming data storage structures on the sidewalls of the first and second stacks; 
 forming a plurality of U-shaped films on the data storage structures and between the stacks, a respective one of the U-shaped films in the plurality having a first pad over the first stack and a second pad over the second stack; 
 depositing a first level of patterned conductors to provide a segment of a reference line connected to the first pad and an inter-level connector connected to the second pad; and 
 depositing a second level of patterned conductors to provide a segment of a bit line, the segment of the bit line including an extension contacting the inter-level connector, 
 wherein the extension comprises a fin having sides aligned with the segment of the bit line, and having other opposing sides aligned with a second insulating film. 
 
     
     
       14. The method of  claim 13  further comprising:
 depositing a first insulating film and a second insulating film over the first level; 
 patterning a hole in the second insulating film; 
 depositing a third insulating film over the patterned second insulating film; 
 patterning a strip in the third insulting film; 
 removing portions of the first, second and third insulating films to expose the top surface of the inter-level connector; and 
 filling the removed portions of the first, second and third insulating films with a conductive material layer. 
 
     
     
       15. The method of  claim 14  further comprising polishing the conductive material layer to expose the third insulating film. 
     
     
       16. The method of  claim 14 , wherein the second insulating film can be silicon nitride or silicon carbide. 
     
     
       17. The method of  claim 14 , wherein the extension comprises a fin within the first and second insulating films.