Method for manufacturing fin structure

Abstract

A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.

We claim: 
     
       1. A method for manufacturing a fin structure, comprising:
 forming a patterned pattern transfer layer on a substrate; 
 forming a first spacer on sidewalls of the pattern transfer layer with the same material as the pattern transfer layer; 
 forming a second spacer on sidewalls of the first spacer; 
 selectively removing the pattern transfer layer and the first spacer at the same time; and 
 patterning the substrate with the second spacer as a mask, so as to form an initial fin with a reduced Line Edge Roughness (LER). 
 
     
     
       2. The method of  claim 1 , wherein the substrate comprises Si, the pattern transfer layer and the first spacer each comprise amorphous silicon, and the method further comprises: forming a stop layer on the substrate, on which the pattern transfer layer is formed. 
     
     
       3. The method of  claim 2 , wherein the second spacer comprises nitride, and the stop layer comprises oxide. 
     
     
       4. The method of  claim 1 , wherein the second spacer comprises a material different from that for the pattern transfer layer and the first spacer. 
     
     
       5. The method of  claim 1 , wherein each of the pattern transfer layer, the first spacer, and the second spacer comprises one selected from amorphous silicon, polycrystalline silicon, oxide, and nitride. 
     
     
       6. The method of  claim 1 , wherein after the initial fin is formed, the method further comprises:
 forming a dielectric layer on the substrate to cover the initial fin; 
 planarizing the dielectric layer by sputtering; and 
 further etching back the dielectric layer to expose a portion of the initial fin, the exposed portion serving as a fin. 
 
     
     
       7. The method of  claim 6 , wherein after the further etching-back, the method further comprises: performing ion implantation to form a punch-through stopper in a portion of the initial fin which is located below a surface of the further etched-back dielectric layer. 
     
     
       8. The method of  claim 7 , wherein after the ion implantation, the method further comprises:
 forming a sacrificial gate stack across the fin on the dielectric layer; 
 selectively etching the initial fin with the sacrificial gate stack as a mask, until the punch-through stopper is exposed; 
 forming a semiconductor layer on exposed portions of the initial fin to form source/drain regions; and 
 replacing the sacrificial gate stack with a gate stack. 
 
     
     
       9. The method of  claim 8 , wherein forming the sacrificial gate stack comprises:
 forming a sacrificial gate dielectric layer; 
 forming a sacrificial gate conductor layer on the sacrificial gate dielectric layer to cover the fin; 
 planarizing the sacrificial gate conductor layer by sputtering; and 
 patterning the gate conductor layer to form the sacrificial gate stack. 
 
     
     
       10. The method of  claim 8 , wherein the semiconductor layer is compressive stressed for a P-type device, and the semiconductor layer is tensile stressed for an N-type device. 
     
     
       11. The method of  claim 10 , wherein the substrate comprises Si, the initial fin is formed by patterning the substrate, and the semiconductor layer comprises SiGe or Si:C. 
     
     
       12. The method of  claim 8 , wherein the semiconductor layer is in-situ doped while being formed.