Multiple-time programmable memory

Abstract

A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.

What is claimed is: 
     
       1. A multiple-time programmable (MTP) memory structure, comprising:
 a first transistor; 
 a second transistor comprising a first source/drain region directly coupled to a first source/drain region of the first transistor at a node; 
 a third transistor operably coupled between the node and a bit line; 
 a fourth transistor operably coupled between the bit line and a voltage source and operably coupled between the third transistor and the voltage source; 
 a first circuit configured to induce a first constant voltage at a second source/drain region of the first transistor; and 
 a second circuit configured to induce a second constant voltage at a gate of the fourth transistor. 
 
     
     
       2. The MTP memory structure of  claim 1 , comprising a fifth transistor operably coupled between the fourth transistor and the voltage source. 
     
     
       3. The MTP memory structure of  claim 1 , the third transistor comprising a P-type metal-oxide-semiconductor (PMOS) transistor. 
     
     
       4. The MTP memory structure of  claim 1 , the first transistor comprising an N-type metal-oxide-semiconductor (NMOS) transistor. 
     
     
       5. The MTP memory structure of  claim 1 , the fourth transistor comprising an NMOS transistor. 
     
     
       6. The MTP memory structure of  claim 1 , the second transistor comprising an NMOS transistor. 
     
     
       7. The MTP memory structure of  claim 2 , the fifth transistor comprising a floating gate metal-oxide-semiconductor field-effect transistor (MOSFET). 
     
     
       8. The MTP memory structure of  claim 1 , the gate of the fourth transistor connected to a control signal. 
     
     
       9. The MTP memory structure of  claim 2 , a gate of the fifth transistor connected to a word line. 
     
     
       10. The MTP memory structure of  claim 1 , a first source/drain of the third transistor directly coupled to the first source/drain region of the first transistor at the node. 
     
     
       11. A CMOS multiple-time programmable (MTP) memory structure, comprising:
 a first transistor, a second transistor and a third transistor; 
 a first circuit configured to induce a first constant voltage at a drain of the first transistor; 
 a second circuit configured to induce a second constant voltage at a gate of the second transistor; 
 a third circuit configured to induce a third constant voltage at a gate of the third transistor; 
 a first voltage source; and 
 a fourth circuit configured to induce a fourth voltage on the third circuit when a voltage provided by the first voltage source is below a first specified voltage. 
 
     
     
       12. The CMOS MTP memory structure of  claim 11 , a voltage provided by the first voltage source substantially equal to 1.5 volts. 
     
     
       13. The CMOS MTP memory structure of  claim 11 , comprising a floating gate transistor, a source of the floating gate transistor connected to a second voltage source. 
     
     
       14. A multiple-time programmable (MTP) memory structure, comprising:
 a first transistor comprising a first source/drain region coupled to a voltage source and a second source/drain region coupled to an output terminal; 
 a second transistor comprising a first source/drain region coupled to a power regulator circuit and a second source/drain region coupled to the output terminal; 
 a third transistor comprising a first source/drain region coupled to the output terminal and a second source/drain region coupled to a bitline; 
 a fourth transistor comprising a first source/drain region coupled to the bitline; and 
 a fifth transistor comprising a first source/drain region coupled to a second source/drain region of the fourth transistor and a second source/drain region coupled to a second voltage source, wherein:
 the first source/drain region of the fourth transistor is coupled to the bitline via a first coupling; 
 the first source/drain region of the fifth transistor is coupled to the second source/drain region of the fourth transistor via a second coupling; 
 the first coupling does not comprise the second source/drain region of the fourth transistor; and 
 the second coupling does not comprise the first source/drain region of the fourth transistor. 
 
 
     
     
       15. The MTP memory structure of  claim 14 , wherein the first transistor is a first-type transistor and the second transistor is a second-type transistor different than the first-type transistor. 
     
     
       16. The MTP memory structure of  claim 14 , wherein the first transistor is a P-type metal-oxide-semiconductor (PMOS) transistor and the second transistor is an N-type metal-oxide-semiconductor (NMOS) transistor. 
     
     
       17. The MTP memory structure of  claim 14 , wherein a gate of the fifth transistor is coupled to a wordline. 
     
     
       18. The MTP memory structure of  claim 14 , wherein the fifth transistor comprises a floating gate metal-oxide-semiconductor field-effect transistor (MOSFET). 
     
     
       19. The MTP memory structure of  claim 1 , a first source/drain of the third transistor directly coupled to the first source/drain region of the first transistor at the node and a second source/drain of the third transistor directly coupled to the bit line. 
     
     
       20. The MTP memory structure of  claim 19 , a first source/drain region of the fourth transistor directly coupled to the bit line.